-
公开(公告)号：US20180005684A1
公开(公告)日：2018-01-04
申请号：US15389751
申请日：2016-12-23
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Antonino Conte , Enrico Castaldo , Raul Andres Bianchi , Francesco La Rosa
IPC: G11C11/24
Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.
-
公开(公告)号：US11495609B2
公开(公告)日：2022-11-08
申请号：US17092551
申请日：2020-11-09
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Fausto Piazza , Sebastien Lagrasta , Raul Andres Bianchi , Simon Jeannot
IPC: H01L27/11546 , H01L21/28 , H01L27/06 , H01L49/02 , H01L21/02 , H01L21/3205 , H01L21/3213 , H01L27/11521 , H01L29/49 , H01L29/66 , H01L21/8234 , H01L27/11541
Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
-
公开(公告)号：US11183468B2
公开(公告)日：2021-11-23
申请号：US15638883
申请日：2017-06-30
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Sebastien Petitdidier , Nicolas Hotellier , Raul Andres Bianchi , Alexis Farcy , Benoît Froment
IPC: H01L23/00 , H01L49/02 , H01L23/498 , H01L23/64 , H01L23/58 , H01L23/48 , H01L21/768 , H01L21/311 , H01L23/29 , H01L23/31 , H01L23/522 , H01L23/528 , H03K3/3565
Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.
-
公开(公告)号：US09978764B2
公开(公告)日：2018-05-22
申请号：US15133394
申请日：2016-04-20
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Fausto Piazza , Sebastien Lagrasta , Raul Andres Bianchi , Simon Jeannot
IPC: H01L27/115 , H01L27/11546 , H01L21/02 , H01L21/28 , H01L21/3205 , H01L21/3213 , H01L27/11521 , H01L49/02 , H01L29/49 , H01L29/66 , H01L27/06 , H01L21/8234 , H01L27/11541
CPC classification number: H01L27/11546 , H01L21/02164 , H01L21/0217 , H01L21/28035 , H01L21/28273 , H01L21/32055 , H01L21/32133 , H01L21/823468 , H01L27/0629 , H01L27/11521 , H01L27/11541 , H01L28/00 , H01L28/60 , H01L29/4916 , H01L29/6656 , H01L29/66825
Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
-
15.发明申请公开(公告)号：US20180003761A1
公开(公告)日：2018-01-04
申请号：US15387370
申请日：2016-12-21
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Antonino Conte , Enrico Castaldo , Raul Andres Bianchi , Francesco La Rosa
CPC classification number: G01R31/028 , G01R31/2882 , G04F10/10
Abstract: A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.
-
Patent Agency Ranking
16.发明授权公开(公告)号：US09117876B2
公开(公告)日：2015-08-25
申请号：US14447699
申请日：2014-07-31
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Grégory Bidal , Laurent Favennec , Raul Andres Bianchi
IPC: H01L21/336 , H01L21/762 , H01L29/51 , H01L29/66 , H01L21/28 , H01L29/49 , H01L29/78
CPC classification number: H01L21/76224 , H01L21/28079 , H01L21/28088 , H01L21/28202 , H01L21/76232 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66477 , H01L29/78
Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.
Abstract translation: 一种集成电路，其包括限定由单晶半导体材料制成的有源区域的至少一个隔离沟槽，所述或每个沟槽包括上部，该上部包括封装沟槽的下部的绝缘层，所述下部至少部分地被埋置 在活性区域和包含氮或碳的包封层。
-
公开(公告)号：US12087873B2
公开(公告)日：2024-09-10
申请号：US17702186
申请日：2022-03-23
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Antonin Zimmer , Dominique Golanski , Raul Andres Bianchi
IPC: H01L31/107
CPC classification number: H01L31/107
Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.
-
公开(公告)号：US12087708B2
公开(公告)日：2024-09-10
申请号：US17451718
申请日：2021-10-21
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Sebastien Petitdidier , Nicolas Hotellier , Raul Andres Bianchi , Alexis Farcy , Benoit Froment
IPC: H01L23/00 , H01L21/311 , H01L21/768 , H01L23/29 , H01L23/31 , H01L23/48 , H01L23/498 , H01L23/522 , H01L23/528 , H01L23/58 , H01L23/64 , H03K3/3565
CPC classification number: H01L23/576 , H01L21/31111 , H01L21/76802 , H01L21/76831 , H01L21/76877 , H01L21/76898 , H01L23/291 , H01L23/3171 , H01L23/481 , H01L23/49855 , H01L23/5226 , H01L23/528 , H01L23/57 , H01L23/573 , H01L23/585 , H01L23/642 , H03K3/3565 , H01L23/293
Abstract: A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.
-
公开(公告)号：US12051705B2
公开(公告)日：2024-07-30
申请号：US17471049
申请日：2021-09-09
Inventor： Raul Andres Bianchi , Marios Barlas , Alexandre Lopez , Bastien Mamdy , Bruce Rae , Isobel Nicholson
IPC: H01L27/146 , G02B5/18
CPC classification number: H01L27/14605 , H01L27/1462 , G02B5/18 , G02B5/1814 , G02B5/1819 , G02B5/1828 , G02B5/1842 , H01L27/14607 , H01L27/1461 , H01L27/1463 , H01L27/1464
Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.
-
公开(公告)号：US10281512B2
公开(公告)日：2019-05-07
申请号：US15387370
申请日：2016-12-21
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Antonino Conte , Enrico Castaldo , Raul Andres Bianchi , Francesco La Rosa
Abstract: A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.
-
-
-
-
-
-
-
-
-
Search Results
23
records
(took 0.021 seconds)
