公开(公告)号：US11380636B2

公开(公告)日：2022-07-05

申请号：US16293239

申请日：2019-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Min Baek ,  Yoon Su Kim ,  Seok Il Hong ,  Byung Lyul Park ,  Sung Han

IPC: H01L23/00

Abstract: A semiconductor package includes a semiconductor chip, and including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad of the semiconductor chip and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening, an encapsulant covering at least a portion of the semiconductor chip, and a connection structure disposed on the active surface of the semiconductor chip, and including a connection via connected to the connection pad in the first opening and the second opening and a redistribution layer electrically connected to the connection pad through the connection via. The second opening has a width narrower than a width of the first opening.

公开(公告)号：US10770447B2

公开(公告)日：2020-09-08

申请号：US16400465

申请日：2019-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Jin Lee ,  Seok Ho Kim ,  Kwang Jin Moon ,  Byung Lyul Park ,  Nae In Lee

IPC: H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/67

Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.

公开(公告)号：US10325897B2

公开(公告)日：2019-06-18

申请号：US15705427

申请日：2017-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Jin Lee ,  Seok Ho Kim ,  Kwang Jin Moon ,  Byung Lyul Park ,  Nae In Lee

IPC: H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67

Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.

公开(公告)号：US10199366B2

公开(公告)日：2019-02-05

申请号：US15627536

申请日：2017-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungwon Kim ,  Su-Jin Kwon ,  Junwon Han ,  Hyunwoo Kim ,  Byung Lyul Park

IPC: H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: A method of manufacturing a semiconductor package, the method including forming a hole that penetrates an interconnect substrate; providing a first carrier substrate below the interconnect substrate; providing a semiconductor chip in the hole; forming a molding layer by coating a molding composition on the semiconductor chip and the interconnect substrate; adhering a second carrier substrate onto the molding layer with an adhesive layer; removing the first carrier substrate to expose a bottom surface of the semiconductor chip and a bottom surface of the interconnect substrate; forming a redistribution substrate below the semiconductor chip and the interconnect substrate; detaching the second carrier substrate from the adhesive layer; and removing the adhesive layer.

公开(公告)号：US09543200B2

公开(公告)日：2017-01-10

申请号：US14183817

申请日：2014-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kunsang Park ,  Sukyoung Kim ,  Jisoon Park ,  Ju-Il Choi ,  Byung Lyul Park ,  Gilheyun Choi

IPC: H01L21/768

CPC classification number: H01L21/76864 ,  H01L21/76873 ,  H01L21/76898

Abstract: Methods for fabricating semiconductor devices having through electrodes are provided. The method may comprise forming a via hole which opens towards an upper surface of a substrate and disconnects with a lower surface of the substrate; forming a via isolation layer which extends along an inner surface of the via hole and covers the upper surface of the substrate; forming a seed layer on the via isolation layer which extends along the via isolation layer; annealing the seed layer in-situ after forming the seed layer; forming a conductive layer, filling the via hole, by an electroplating using the seed layer; and planarizing the upper surface of the substrate to form a through electrode surrounded by the via isolation layer in the via hole.

Abstract translation: 提供了具有通孔电极的制造半导体器件的方法。 该方法可以包括形成朝向衬底的上表面打开并且与衬底的下表面断开的通孔; 形成沿所述通孔的内表面延伸并覆盖所述基板的上表面的通孔隔离层; 在沿通孔隔离层延伸的通孔隔离层上形成晶种层; 在形成种子层之后，原位退火晶种层; 通过使用种子层的电镀形成导电层，填充所述通孔; 并且平坦化衬底的上表面以形成由通孔中的通孔隔离层包围的通孔。

公开(公告)号：US10651074B2

公开(公告)日：2020-05-12

申请号：US15595948

申请日：2017-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Hwan Kim ,  Taewoo Kang ,  Byung Lyul Park ,  Hyungjun Jeon

IPC: H01L21/683 ,  B65G47/91 ,  C23C16/458 ,  H01L21/67 ,  H01L21/687

Abstract: A substrate processing apparatus may include a substrate jig device and a transfer unit, which is configured to hold a substrate in a non-contact state and move the substrate toward the substrate jig device. The substrate jig device may include a supporter, which is configured to support an edge of the substrate and have an opening, a first suction part, which overlaps with a center region of the opening and is configured to move in a first direction, and a plurality of second suction parts, which overlap with an edge region of the opening and are configured to move toward the opening. Here, the first direction may be a direction passing through the opening.

公开(公告)号：US09502274B2

公开(公告)日：2016-11-22

申请号：US14281880

申请日：2014-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi Koan Hong ,  Byung Lyul Park ,  Jumyong Park ,  Jisoon Park ,  Kyu-Ha Lee ,  Siyoung Choi

IPC: H01L21/673

CPC classification number: H01L21/6733 ,  H01L21/6732 ,  H01L21/67323 ,  H01L21/67326

Abstract: Embodiments of the present inventive concepts provide a wafer loader having one or more buffer zones to prevent damage to a wafer loaded in the wafer loader. The wafer loader may include a plurality of loading sections that protrude from a main body and are configured to be arranged at various locations along an edge of the wafer. Each of the loading sections may include a groove into which the edge of the wafer may be inserted. The loading section may include first and second protrusions having first and second inner sides, respectively, that face each other to define the groove therebetween. At least one of the first and second inner sides may include a recess to define the buffer zone.

Abstract translation: 本发明构思的实施例提供了具有一个或多个缓冲区的晶片装载器，以防止损坏装载在晶片装载器中的晶片。 晶片装载机可以包括从主体突出的多个装载部分，并被构造成沿着晶片的边缘布置在不同位置。 每个加载部分可以包括槽，其中可以插入晶片的边缘。 装载部分可以包括分别具有彼此面对以限定其间的凹槽的第一和第二内侧的第一和第二突起。 第一和第二内侧中的至少一个可以包括限定缓冲区的凹部。

公开(公告)号：US09496163B2

公开(公告)日：2016-11-15

申请号：US14505774

申请日：2014-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： HyungJun Jeon ,  Byung Lyul Park ,  Jisoon Park

IPC: H01L23/495 ,  H01L21/683 ,  H01L21/304 ,  H01L21/768

CPC classification number: H01L21/6835 ,  H01L21/304 ,  H01L21/6836 ,  H01L21/76898 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a carrier and a method of fabricating a semiconductor device using the same. The carrier may include a recess region provided adjacent to an edge thereof. The recess region may be configured to confine an adhesive layer within a desired region including the recess region. The recess region makes it possible to reduce a process failure in a process of fabricating a semiconductor device.

Abstract translation: 提供一种使用其制造半导体器件的载体和方法。 载体可以包括邻近其边缘设置的凹陷区域。 凹部区域可以被配置为将粘合剂层限制在包括凹部区域的期望区域内。 凹部区域可以减少制造半导体器件的工艺过程中的故障。

公开(公告)号：US08927426B2

公开(公告)日：2015-01-06

申请号：US13766326

申请日：2013-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Pil-Kyu Kang ,  Kyu-Ha Lee ,  Gilheyun Choi ,  YongSoon Choi ,  Byung Lyul Park ,  Hyunsoo Chung

IPC: H01L21/302 ,  H01L29/40 ,  H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Semiconductor devices having through-vias and methods for fabricating the same are described. The method may include forming a hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a sacrificial layer partially filling the hole, forming a through-via in the hole partially filled with the sacrificial layer, forming a via-insulating layer between the through-via and the substrate, and exposing the through-via through a bottom surface of the substrate. Forming the sacrificial layer may include forming an insulating flowable layer on the substrate, and constricting the insulating flowable layer to form a solidified flowable layer.

Abstract translation: 描述了具有通孔的半导体器件及其制造方法。 该方法可以包括形成朝向衬底的顶表面打开并部分地穿透衬底的孔，形成部分填充孔的牺牲层，在部分填充有牺牲层的孔中形成通孔，形成通孔绝缘 通孔和衬底之间的层，并且使通孔穿过衬底的底表面。 形成牺牲层可以包括在衬底上形成绝缘的可流动层，并且收缩绝缘流动层以形成固化的可流动层。

公开(公告)号：US08872351B2

公开(公告)日：2014-10-28

申请号：US13756833

申请日：2013-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangjin Moon ,  SuKyoung Kim ,  Kunsang Park ,  Byung Lyul Park ,  Sukchul Bang ,  Jin Ho An ,  Kyu-Ha Lee ,  Dosun Lee ,  Gilheyun Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/04 ,  H01L23/12 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode.

Abstract translation: 提供具有通孔的半导体器件及其制造方法。 所述方法可以包括形成至少部分地穿透基板的通孔，所述通孔具有设置在所述基板的顶表面上的入口，形成通孔绝缘层以保形地覆盖所述通孔的内表面，形成缓冲器 所述缓冲层由收缩性优于所述通孔绝缘层的材料形成，形成贯通电极以填充所述通孔，所述通孔设置在所述通孔绝缘层上， 与缓冲层一起凹陷基底的底表面以露出通孔。