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公开(公告)号：US09558821B2
公开(公告)日：2017-01-31
申请号：US14645701
申请日：2015-03-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Dae-Seok Byeon , Yeong-Taek Lee , Hyo-Jin Kwon , Yong-Kyu Lee
CPC classification number: G11C13/0069 , G11C11/1659 , G11C11/1675 , G11C11/5607 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0064 , G11C13/0097 , G11C2013/0076 , G11C2213/71
Abstract: Provided are a resistive memory device and a method of the resistive memory device. The method of operating the resistive memory device includes performing a pre-read operation on memory cells in response to a write command; performing an erase operation on one or more first memory cells on which a reset write operation is to be performed, determined based on a result of comparing pre-read data from the pre-read operation with write data; and performing set-direction programming on at least some memory cells from among the erased one or more first memory cells and on one or more second memory cells on which a set write operation is to be performed.
Abstract translation: 提供了电阻式存储器件和电阻式存储器件的方法。 操作电阻式存储器件的方法包括：响应写入命令对存储器单元执行预读取操作; 基于将来自预读取操作的预读数据与写数据进行比较确定的一个或多个要执行复位写操作的第一存储单元执行擦除操作; 并且对被擦除的一个或多个第一存储器单元中的至少一些存储器单元以及要执行设定写入操作的一个或多个第二存储器单元执行设置方向编程。
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公开(公告)号：US09536605B2
公开(公告)日：2017-01-03
申请号：US14806780
申请日：2015-07-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Yeong-Taek Lee , Dae-Seok Byeon , Bo-Geun Kim
CPC classification number: G11C13/004 , G11C11/1659 , G11C11/1673 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0061 , G11C2013/0054 , G11C2213/71 , G11C2213/77
Abstract: Provided are a resistive memory device including a plurality of memory cells, and a method of operating the resistive memory device. The resistive memory device includes a sensing circuit connected to a first signal line, to which a memory cell is connected, the sensing circuit sensing data stored in the memory cell based on a first reference current; and a reference time generator for generating a reference time signal that determines a time point when a result of the sensing is to be output, based on the first reference current.
Abstract translation: 提供了包括多个存储单元的电阻式存储器件以及操作该电阻式存储器件的方法。 电阻式存储器件包括连接到存储单元连接到的第一信号线的感测电路，感测电路基于第一参考电流感测存储在存储器单元中的数据; 以及参考时间发生器，用于产生基于所述第一参考电流确定所述感测的结果的时间点的参考时间信号。
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公开(公告)号：US09305608B2
公开(公告)日：2016-04-05
申请号：US14637647
申请日：2015-03-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park
IPC: G11C5/06 , G11C13/00 , G11C11/4094 , G11C11/4097 , G11C11/4099
CPC classification number: G11C5/06 , G11C7/12 , G11C7/18 , G11C11/165 , G11C11/1655 , G11C11/1673 , G11C11/1675 , G11C11/4094 , G11C11/4097 , G11C11/4099 , G11C13/0002 , G11C13/0004 , G11C13/0021 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0092 , G11C2213/71
Abstract: A memory device may including a first local bit line electrically connected with a first memory cell, a first global bit line electrically connected with the first local bit line, a second local bit line electrically connected with a second memory cell, and a second global bit line electrically connected with the second local bit line. The first global bit line is primarily charged with electric charge. The first global bit line and the second global bit line share the primarily charged electric charge. The second global bit line is secondarily charged with the electric charge.
Abstract translation: 存储器件可以包括与第一存储器单元电连接的第一本地位线，与第一局部位线电连接的第一全局位线，与第二存储单元电连接的第二局部位线，以及第二全局位 线与第二局部位线电连接。 第一个全局位线主要由电荷充电。 第一个全局位线和第二个全局位线共享主要充电的电荷。 第二个全局位线被二次充电。
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公开(公告)号：US09171617B1
公开(公告)日：2015-10-27
申请号：US14667993
申请日：2015-03-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyo-Jin Kwon
CPC classification number: G11C13/0069 , G11C13/0002 , G11C13/0064 , G11C2013/0066 , G11C2013/0076 , G11C2013/0092
Abstract: A method of programming memory cells of a resistive memory device includes; applying a first current pulse to each of the plurality of memory cells; applying a second current pulse that increases by a first difference compared to the first current pulse to each of the plurality of memory cells to which the first current pulse is applied; and applying a third current pulse that increases by a second difference compared to the second current pulse to each of the plurality of memory cells to which the second current pulse is applied, wherein the first through third current pulses non-linearly increase, and the second difference is greater than the first difference.
Abstract translation: 一种编程电阻式存储器件的存储单元的方法包括： 对所述多个存储单元中的每一个施加第一电流脉冲; 将与第一电流脉冲相比增加第一差的第二电流脉冲施加到施加了第一电流脉冲的多个存储单元中的每一个; 以及将与所述第二电流脉冲相比增加第二差的第三电流脉冲施加到施加所述第二电流脉冲的所述多个存储单元中的每一个，其中所述第一至第三电流脉冲非线性增加，并且所述第二电流脉冲 差异大于第一个差异。
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公开(公告)号：US09613697B2
公开(公告)日：2017-04-04
申请号：US15151661
申请日：2016-05-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Yeong-Taek Lee , Dae-Seok Byeon
CPC classification number: G11C13/0069 , G11C11/56 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C2013/0078 , G11C2213/15 , G11C2213/71 , G11C2213/72 , G11C2213/79
Abstract: A resistive memory device includes a memory cell array having a plurality of memory cells respectively connected to a plurality of first signal lines and a plurality of second signal lines crossing each other. A first write driver is configured to provide a write voltage to write data to the memory cells. A second write driver is configured to be disposed between the memory cell array and the first write driver and provide a write current generated based on the write voltage to a first signal line selected from among the plurality of first signal lines.
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Patent Agency Ranking
16.发明授权Resistive memory device having memory cell arrays with multiple stack layers and bad-region managing circuit and method for managing short failure 有权具有具有多个堆叠层的存储单元阵列和不良区域管理电路的电阻式存储器件以及用于管理短路故障的方法公开(公告)号：US09570200B2
公开(公告)日：2017-02-14
申请号：US14743521
申请日：2015-06-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Jin Kwon , Dae-Seok Byeon , Yeong-Taek Lee , Chi-Weon Yoon , Yong-Kyu Lee , Hyun-Kook Park
CPC classification number: G11C29/76 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1677 , G11C11/1695 , G11C13/0002 , G11C13/0023 , G11C13/0059 , G11C13/0064 , G11C13/0069 , G11C29/808 , G11C2029/4402 , G11C2213/71
Abstract: A resistive memory device includes a memory cell array that includes a plurality of memory layers stacked in a vertical direction. Each of the plurality of memory layers includes a plurality of memory cells disposed in regions where a plurality of first lines and a plurality of second lines cross each other. A bad region management unit defines as a bad region a first memory layer including a bad cell from among the plurality of memory cells and at least one second memory layer.
Abstract translation: 电阻式存储器件包括存储单元阵列，其包括沿垂直方向堆叠的多个存储层。 多个存储层中的每一个包括设置在多个第一线和多条第二线彼此交叉的区域中的多个存储单元。 不良区域管理单元将包括来自多个存储器单元中的不良单元和至少一个第二存储器层的第一存储器层定义为不良区域。
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公开(公告)号：US09472275B2
公开(公告)日：2016-10-18
申请号：US14698175
申请日：2015-04-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Young-Hoon Oh , Dae-Seok Byeon , Yong-Kyu Lee , Hyo-Jin Kwon
CPC classification number: G11C13/004 , G06F11/00 , G06F11/1048 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C2013/0045 , G11C2013/0054
Abstract: A memory device and a method of operating the memory device are provided for performing a read-retry operation. The method of operating the memory device includes starting a read-retry mode, reading data of multiple cell regions using different read conditions, and setting a final read condition for the cell regions according to results of data determination operations on data read from the cell regions.
Abstract translation: 提供了一种用于执行读取重试操作的存储器件和操作存储器件的方法。 操作存储装置的方法包括开始读取重试模式，使用不同的读取条件读取多个单元区域的数据，并且根据从单元区域读取的数据的数据确定操作的结果来设置单元区域的最终读取条件 。
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18.发明授权Resistive memory device and method of operating the same to reduce leakage current 有权电阻式存储器件及其操作方法，以减少漏电流公开(公告)号：US09361974B2
公开(公告)日：2016-06-07
申请号：US14683269
申请日：2015-04-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Kyu Lee , Dae-Seok Byeon , Yeong-Taek Lee , Chi-Weon Yoon , Hyun-Kook Park , Hyo-Jin Kwon
CPC classification number: G11C13/0023 , G11C13/0033 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/0078
Abstract: A method of operating a memory device includes determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among a plurality of first signal lines; dividing an array of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to unselected ones of second signal lines included in the n blocks. Each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line.
Abstract translation: 一种操作存储器件的方法包括从多个第一信号线中确定流过所选择的第一信号线的工作电流的值，所述第一信号线被施加选择电压; 将存储单元阵列划分为n个块，n是大于1的整数，基于工作电流的值; 以及将对应于n个块的具有不同电压电平的抑制电压施加到包括在n个块中的未选择的第二信号线。 每个未选择的第二信号线是由于流过所选择的第一信号线的工作电流和由未选择的第二信号线和所选择的第一信号线寻址的存储器单元而引起的漏电流可能流过的通路。
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19.发明授权Resistive memory device, resistive memory system, and method of operating resistive memory device 有权电阻式存储器件，电阻式存储器系统和操作电阻式存储器件的方法公开(公告)号：US09269429B2
公开(公告)日：2016-02-23
申请号：US14665127
申请日：2015-03-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Dae-Seok Byeon , Yeong-Taek Lee , Bo-Geun Kim , Yong-Kyu Lee , Hyo-Jin Kwon
CPC classification number: G11C13/0069 , G11C5/025 , G11C13/0023 , G11C13/0033 , G11C2213/71
Abstract: A resistive memory device includes a memory cell array including a plurality vertically stacked layers having one layer designated as an interference-free layer and another layer designated as an access prohibited layer, wherein the interference-free layer and the access prohibited layer share a connection with at least one signal line and access operations directed to memory cells the access prohibited layer are prohibited.
Abstract translation: 电阻式存储器件包括存储单元阵列，该存储单元阵列包括多个垂直层叠的层，其中一层被指定为无干扰层，另一层指定为禁止访问层，其中无干扰层和禁止访问层共享与 禁止至少一条信号线和针对存储器单元访问禁止层的访问操作。
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公开(公告)号：US08988929B2
公开(公告)日：2015-03-24
申请号：US14093076
申请日：2013-11-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun-Kook Park , Young-Don Choi
CPC classification number: G11C13/004 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C2013/0052 , G11C2213/71 , G11C2213/72
Abstract: A method is for driving a nonvolatile memory device, where the nonvolatile memory device includes a memory cell array composed of resistance memory cells. The method includes electrically connecting a clamping circuit, a line resistor and a selected one of the resistance memory cells in series between a sensing node and a ground. The method further includes adjusting at least one of a clamping voltage of the clamping circuit and a resistance of the line resistor according to a relative location of the selected one of the resistance memory cells within the memory cell array, and applying a read current to the sense node and sensing a voltage of the sense node to read a data stored in the selected one of the resistance memory cells.
Abstract translation: 一种用于驱动非易失性存储器件的方法，其中非易失性存储器件包括由电阻存储器单元组成的存储单元阵列。 该方法包括将感测节点和接地之间的串联的钳位电路，线路电阻器和所选择的电阻存储器单元电连接。 该方法还包括根据存储单元阵列内所选择的一个电阻存储器单元的相对位置来调整钳位电路的钳位电压和线路电阻器的电阻中的至少一个，并将读取电流施加到 感测节点并且感测感测节点的电压以读取存储在所选择的一个电阻存储器单元中的数据。
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