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    Memory device and method of determining read voltage of memory device
    11.
    发明授权
    Memory device and method of determining read voltage of memory device 有权
    存储器件和确定存储器件读取电压的方法

    公开(公告)号：US09036412B2

    公开(公告)日：2015-05-19

    申请号：US13908006

    申请日：2013-06-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myung-Hoon Choi ,  Jae-Yong Jeong ,  Ki-Tae Park

    IPC: G11C11/34 ,  G11C16/34 ,  G11C29/42 ,  G11C16/04 ,  G11C16/26 ,  G11C29/02 ,  G11C16/00

    CPC classification number: G11C16/34 ,  G11C16/00 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3431 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42

    Abstract: A method of operating a memory device includes applying an initial read voltage to a selected wordline to perform a read operation on memory cells connected to the selected wordline, determining whether a read failure occurs with respect to one or more of the memory cells, upon determining that a read failure has occurred with respect to some of the memory cells, determining threshold voltage distribution information for distinct groups of the memory cells, and determining a new read voltage to be applied to the selected wordline based on the threshold voltage distribution information.

    Abstract translation: 一种操作存储器件的方法包括将初始读取电压施加到所选择的字线以对连接到所选择的字线的存储器单元执行读取操作，确定在确定存储器单元中的一个或多个时是否发生读取故障 相对于一些存储器单元发生读取失败，确定存储器单元的不同组的阈值电压分布信息，以及基于阈值电压分布信息确定要施加到所选字线的新读取电压。

    Non-volatile memory device and operation method of the same
    13.
    发明授权
    Non-volatile memory device and operation method of the same 有权

    公开(公告)号：US11205484B2

    公开(公告)日：2021-12-21

    申请号：US16752924

    申请日：2020-01-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Soo-Woong Lee ,  Hyun-Jin Kim ,  Jae-Yong Jeong

    IPC: G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/32 ,  G11C16/24

    Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory cells, a page buffer circuit, and a control logic circuit. The page buffer circuit includes a plurality of first page buffers and a plurality of second page buffers, each including a sense latch, a data latch, and a cache latch. The sense latch senses data stored in the memory cell array and dumps the sensed data to the data latch, the data latch dumps the data dumped by the sense latch to the cache latch, and the cache latch transmits the data dumped by the data latch to a data I/O circuit. While the cache latch included in at least one of the plurality of first page buffers is performing a data transmit operation, the data latch included in at least one of the plurality of second page buffers performs a data dumping operation.

    Method of programming a nonvolatile memory device and nonvolatile memory device performing the method
    16.
    发明授权
    Method of programming a nonvolatile memory device and nonvolatile memory device performing the method 有权
    执行该方法的非易失性存储器件和非易失性存储器件的编程方法

    公开(公告)号：US08854879B2

    公开(公告)日：2014-10-07

    申请号：US13755448

    申请日：2013-01-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-Kyo Shim ,  Min-Seok Kim ,  Tae-Young Kim ,  Ki-Tae Park ,  Jae-Yong Jeong

    IPC: G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418

    Abstract: A method of programming a nonvolatile memory device including multi-level cells that store multi-bit data, includes performing a pre-programming operation that programs at least some of the multi-level cells to a plurality of intermediate states which are different from an erased state, and performing a main programming operation that programs the multi-level cells to a plurality of target states corresponding to the multi-bit data. At least some of the intermediate program states have threshold voltage distributions that partially overlap each other.

    Abstract translation: 一种编程包括存储多位数据的多电平单元的非易失性存储器件的方法包括执行将至少一些多电平单元编程为与被擦除的多个等级单元不同的多个中间状态的预编程操作 状态，并且执行将多电平单元编程为对应于多位数据的多个目标状态的主编程操作。 至少一些中间程序状态具有部分彼此重叠的阈值电压分布。

    NONVOLATILE MEMORY DEVICES INCLUDING MEMORY PLANES AND MEMORY SYSTEMS INCLUDING THE SAME
    17.
    发明申请
    NONVOLATILE MEMORY DEVICES INCLUDING MEMORY PLANES AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20200168277A1

    公开(公告)日：2020-05-28

    申请号：US16432959

    申请日：2019-06-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Jin Kim ,  Chung-Ho Yu ,  Yong-Kyu Lee ,  Jae-Yong Jeong

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

    Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

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