公开(公告)号：US11791137B2

公开(公告)日：2023-10-17

申请号：US16855048

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Ho-Jin Lee ,  Dong-Chan Lim ,  Jinnam Kim ,  Kwangjin Moon

IPC: H01J37/32 ,  H01L21/67

CPC classification number: H01J37/32642 ,  H01J37/32715 ,  H01L21/67069 ,  H01J2237/334

Abstract: A bevel etching apparatus includes a chuck plate that is configured to receive a substrate, a lower ring surrounding a circumference of the chuck plate, a cover plate on the chuck plate, and an upper ring surrounding a circumference of the cover plate. The lower ring includes a ring base and a protrusion that extends upwardly from an edge of the ring base and surrounds a lower portion of a sidewall of the substrate.

公开(公告)号：US11749586B2

公开(公告)日：2023-09-05

申请号：US17514218

申请日：2021-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sonkwan Hwang ,  Taeseong Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Hyungjun Jeon

IPC: H01L21/00 ,  H01L23/48 ,  H01L27/088 ,  H01L25/065 ,  H01L21/768 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L25/0657 ,  H01L27/0886 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.

公开(公告)号：US11373932B2

公开(公告)日：2022-06-28

申请号：US16750579

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoukyung Cho ,  Daesuk Lee ,  Jinnam Kim ,  Taeseong Kim ,  Kwangjin Moon ,  Hakseung Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L23/528 ,  H01L21/027 ,  H01L21/288 ,  H01L21/321

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first wiring layer, a first semiconductor substrate on the first wiring layer, a first dielectric layer on the first semiconductor substrate, a landing pad in the first wiring layer, a through hole that penetrates the first semiconductor substrate, the first dielectric layer, and the first wiring layer and exposes the landing pad, the through hole including a first hole and a second hole on a bottom end of the first hole, the second hole having a maximum diameter less than a minimum diameter of the first hole, and a mask layer on an upper lateral surface of the through hole.

公开(公告)号：US11133240B2

公开(公告)日：2021-09-28

申请号：US16794782

申请日：2020-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Jinnam Kim ,  Kwangjin Moon ,  Eunji Kim ,  Taeseong Kim ,  Sangjun Park

IPC: H01L23/48 ,  H01L25/18 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate including at least one semiconductor structure, an interlayer insulating layer disposed on the semiconductor substrate, at least one first via structure penetrating the semiconductor substrate and the interlayer insulating layer, including a first region having a first width at an upper surface of the interlayer insulating layer and a second region extending from the first region and having a second width at a lower surface of the semiconductor substrate, wherein a side surface of the first region and a side surface of the second region have different profiles at a boundary between the first region and the second region, and at least one second via structure penetrating the semiconductor substrate and the interlayer insulating layer and having a third width greater than the first width at an upper surface of the interlayer insulating layer.

公开(公告)号：US20210066386A1

公开(公告)日：2021-03-04

申请号：US16855048

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Ho-Jin Lee ,  Dong-Chan Lim ,  Jinnam Kim ,  Kwangjin Moon

IPC: H01L27/146 ,  H01L21/67 ,  H01J37/32

Abstract: A bevel etching apparatus includes a chuck plate that is configured to receive a substrate, a lower ring surrounding a circumference of the chuck plate, a cover plate on the chuck plate, and an upper ring surrounding a circumference of the cover plate. The lower ring includes a ring base and a protrusion that extends upwardly from an edge of the ring base and surrounds a lower portion of a sidewall of the substrate.

公开(公告)号：US20210043575A1

公开(公告)日：2021-02-11

申请号：US16849085

申请日：2020-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Jinnam Kim ,  Hyoukyung Cho ,  Taeseong Kim ,  Kwangjin Moon

IPC: H01L23/538

Abstract: A semiconductor device may include a first semiconductor substrate having a first surface and a second surface opposite to each other, a first circuit layer provided on the first surface of the first semiconductor substrate, a connection pad provided on the second surface of the first semiconductor substrate, and a first penetration via and a second penetration via penetrating the first semiconductor substrate and at least a portion of the first circuit layer. The first penetration via and the second penetration via may be provided in a first penetration hole and a second penetration hole, respectively. Each of the first and second penetration holes may include a first portion, a second portion, and a third portion. A width of the first portion of the first penetration hole may be smaller than a width of the first portion of the second penetration hole.

公开(公告)号：US20180108540A1

公开(公告)日：2018-04-19

申请号：US15636849

申请日：2017-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun Phee ,  Ho-Jin Lee ,  Taeseong Kim ,  Kwangjin Moon ,  Jin Ho An ,  Naein Lee

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/683 ,  H01L23/64 ,  H01L23/00 ,  H05K3/40 ,  H05K1/16

CPC classification number: H01L21/486 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/544 ,  H01L23/642 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2224/13101 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/14511 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/37001 ,  H05K1/162 ,  H05K3/4038 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A method of manufacturing a semiconductor package including forming a photoresist pattern on a first surface of an interposer substrate. The interposer substrate includes an electrode zone and a scribe line zone. The interposer substrate is etched using the photoresist pattern as a mask to form a first opening and a second opening respectively on the electrode zone and the scribe line zone. An insulation layer and a conductive layer are formed on the first surface of the interposer substrate. A width of the second opening is smaller than a width of the first opening. The insulation layer contacts each of the first surface of the interposer substrate, an inner surface of the first opening, and an inner surface of the second opening.

公开(公告)号：US08710650B2

公开(公告)日：2014-04-29

申请号：US14047548

申请日：2013-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sukchul Bang ,  Kwangjin Moon ,  Byung Lyul Park ,  Dosun Lee ,  Deok-Young Jung ,  Gilheyun Choi

IPC: H01L23/34

CPC classification number: H01L23/5226 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: Provided are semiconductor devices having through electrodes and methods of fabricating the same. The method includes providing a substrate including top and bottom surfaces facing each other, forming a hole and a gap extending from the top surface of the substrate toward the bottom surface of the substrate, the gap surrounding the hole and being shallower than the hole, filling the hole with an insulating material, forming a metal interconnection line on the top surface of the substrate on the insulating material, recessing the bottom surface of the substrate to expose the insulating material, removing the insulating material to expose the metal interconnection line via the hole, filling the hole with a conductive material to form a through electrode connected to the metal interconnection line, recessing the bottom surface of the substrate again to expose the gap, and forming a lower insulating layer on the bottom surface of the substrate.

Abstract translation: 提供了具有通过电极的半导体器件及其制造方法。 所述方法包括提供包括彼此面对的顶表面和底表面的基板，形成从基板的顶表面延伸到基板的底表面的孔和间隙，围绕孔的间隙并且比孔更浅，填充 所述孔具有绝缘材料，在所述绝缘材料的所述基板的顶表面上形成金属互连线，凹陷所述基板的底表面以暴露所述绝缘材料，去除所述绝缘材料以经由所述孔暴露所述金属互连线 用导电材料填充孔以形成连接到金属互连线的通孔，再次使基板的底表面露出以露出间隙，并在基板的底表面上形成下绝缘层。

公开(公告)号：US20140008815A1

公开(公告)日：2014-01-09

申请号：US13911569

申请日：2013-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeun-Sang Park ,  Byung-Lyul Park ,  SungHee Kang ,  Taeseong Kim ,  Kwangjin Moon ,  Sukchul Bang

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Semiconductor devices are disclosed. The semiconductor device may include a semiconductor substrate having a first surface and a second surface opposite to each other and a pad trench formed at a portion of the second surface, a through-electrode penetrating the semiconductor substrate and protruding from a bottom surface of the pad trench. A buried pad may be disposed in the pad trench and may surround the through-electrode.

Abstract translation: 公开了半导体器件。 半导体器件可以包括具有彼此相对的第一表面和第二表面的半导体衬底和形成在第二表面的一部分处的衬垫沟槽，穿透半导体衬底并从衬底的底表面突出的通孔 沟。 掩埋焊盘可以设置在焊盘沟槽中并且可以围绕通孔。

公开(公告)号：US20130200526A1

公开(公告)日：2013-08-08

申请号：US13756833

申请日：2013-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangjin Moon ,  SuKyoung Kim ,  Kunsang Park ,  Byung Lyul Park ,  Sukchul Bang ,  Jin Ho An ,  Kyu-Ha Lee ,  Dosun Lee ,  Gilheyun Choi

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode.

Abstract translation: 提供具有通孔的半导体器件及其制造方法。 所述方法可以包括形成至少部分地穿透基板的通孔，所述通孔具有设置在所述基板的顶表面上的入口，形成通孔绝缘层以保形地覆盖所述通孔的内表面，形成缓冲器 所述缓冲层由收缩性优于所述通孔绝缘层的材料形成，形成贯通电极以填充所述通孔，所述通孔设置在所述通孔绝缘层上， 与缓冲层一起凹陷基底的底表面以露出通孔。