公开(公告)号：US20170230041A1

公开(公告)日：2017-08-10

申请号：US15427815

申请日：2017-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Takanori MATSUZAKI

IPC: H03K5/24 ,  H01L21/78 ,  H01L23/498

CPC classification number: H03K5/2481 ,  G11C5/144 ,  G11C5/145 ,  H01L21/78 ,  H01L23/49844 ,  H01L27/00 ,  H01L27/10805 ,  H01L27/14687 ,  H01L28/00

Abstract: Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential. The first negative potential and the second negative potential are input to a gate of the first transistor and a gate of the second transistor, respectively. Each drain of the first transistor and the second transistor is electrically connected to the load. The third transistor serves as a current source. The first transistor and the second transistor each include a backgate. A positive potential is input to the backgates.

公开(公告)号：US20170186749A1

公开(公告)日：2017-06-29

申请号：US15383274

申请日：2016-12-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuaki OHSHIMA ,  Kiyoshi KATO ,  Tomoaki ATSUMI

IPC: H01L27/105 ,  H01L27/11 ,  H01L27/108 ,  G06F1/32 ,  H01L23/528 ,  G11C5/06 ,  G11C5/14 ,  H01L27/12 ,  H01L23/522

CPC classification number: H01L27/1052 ,  G06F1/3275 ,  G11C5/06 ,  G11C5/14 ,  G11C7/04 ,  G11C11/401 ,  G11C11/4074 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/1108 ,  H01L27/1207 ,  H01L27/1211 ,  H01L27/1225 ,  H01L29/7851 ,  H01L29/78648 ,  H01L29/7869

Abstract: Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.

公开(公告)号：US20170179294A1

公开(公告)日：2017-06-22

申请号：US15380502

申请日：2016-12-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi KATO ,  Tomoaki ATSUMI ,  Shunpei YAMAZAKI ,  Haruyuki BABA ,  Shinpei MATSUDA

IPC: H01L29/786 ,  H01L27/108 ,  H01L27/088

Abstract: A semiconductor device capable of holding data for a long time is provided. The semiconductor device includes a first transistor, a second transistor, and a circuit. The first transistor includes a first gate and a second gate. The first transistor includes a first semiconductor in a channel formation region. The first gate and the second gate overlap with each other in a region with the first semiconductor provided therebetween. The second transistor includes a second semiconductor in a channel formation region. A first terminal of the second transistor is electrically connected to a gate of the second transistor and the second gate. A second terminal of the second transistor is electrically connected to the circuit. The circuit has a function of generating a negative potential. The second semiconductor has a wider bandgap than the first semiconductor.

公开(公告)号：US20150263008A1

公开(公告)日：2015-09-17

申请号：US14643621

申请日：2015-03-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA

IPC: H01L27/108

CPC classification number: H01L27/1156 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/405 ,  G11C11/4085 ,  H01L27/11551 ,  H01L27/1225

Abstract: A novel semiconductor device that can write and read multilevel data is provided. A memory cell includes a bit line, a power supply line, first and second nodes, first to fourth transistors, and first and second capacitors. One of two divided multilevel data is written to the first node through the first transistor. The other of the divided multilevel data is written to the second node through the second transistor. A gate of the third transistor is connected to the first node, and a gate of the fourth transistor is connected to the second node. The third and fourth transistors control electrical continuity between the bit line and the power supply line. Each of the first and second transistors preferably includes an oxide semiconductor in a semiconductor layer.

Abstract translation: 提供了一种可以写入和读取多级数据的新型半导体器件。 存储单元包括位线，电源线，第一和第二节点，第一至第四晶体管以及第一和第二电容器。 两个分割的多电平数据之一通过第一晶体管写入第一节点。 分割的多级数据中的另一个通过第二晶体管写入第二节点。 第三晶体管的栅极连接到第一节点，并且第四晶体管的栅极连接到第二节点。 第三和第四晶体管控制位线和电源线之间的电连续性。 第一和第二晶体管中的每一个优选地包括半导体层中的氧化物半导体。

公开(公告)号：US20150213842A1

公开(公告)日：2015-07-30

申请号：US14678098

申请日：2015-04-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tomoaki ATSUMI ,  Yoshiya TAKEWAKI

IPC: G11C5/10 ,  G11C11/4091 ,  G11C11/406

CPC classification number: G11C5/10 ,  G11C11/401 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4099 ,  H01L27/10873 ,  H01L27/10897 ,  H01L27/1218 ,  H01L27/1225

Abstract: In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.

Abstract translation: 在包括具有排列成矩阵的存储单元的存储单元阵列的存储器模块中，每个存储单元包括使用氧化物半导体的第一晶体管和第一电容器; 包括p沟道第三晶体管，第二电容器和使用氧化物半导体的第二晶体管的参考单元; 以及包括电阻器和比较器的刷新定时检测电路，其中当通过第一晶体管向第一电容器提供电位时，通过第二晶体管将电位提供给第二电容器，其中第三晶体管的漏极电流值 根据存储在第二电容器中的电位而改变，并且其中当第三晶体管的漏极电流值高于给定值时，执行存储单元阵列和参考单元的刷新操作。

公开(公告)号：US20250015088A1

公开(公告)日：2025-01-09

申请号：US18711187

申请日：2022-11-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Koji KUSUNOKI ,  Hideaki SHISHIDO ,  Susumu KAWASHIMA

IPC: H01L27/12

Abstract: A display apparatus with high luminance and a long lifetime is provided. The display apparatus includes a first layer and a second layer positioned above the first layer. The first layer includes a substrate and a plurality of driver circuit regions, and the second layer includes a plurality of display regions. The substrate is a glass substrate. Each of the plurality of driver circuit regions includes a driver circuit, and the driver circuit includes a transistor including silicon in a channel formation region. Each of the plurality of display regions includes a pixel, and the pixel includes a light-emitting diode and a transistor including a metal oxide in a channel formation region. Specifically, the light-emitting diode is preferably a micro light-emitting diode. The driver circuit included in one of the plurality of driver circuit regions has a function of driving the display pixel included in one of the plurality of display regions.

公开(公告)号：US20250008748A1

公开(公告)日：2025-01-02

申请号：US18885848

申请日：2024-09-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/408 ,  H01L27/06 ,  H01L29/24 ,  H01L29/786 ,  H10B41/20 ,  H10B41/70

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US20240413141A1

公开(公告)日：2024-12-12

申请号：US18700899

申请日：2022-10-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tomoaki ATSUMI ,  Koji KUSUNOKI ,  Hideaki SHISHIDO ,  Susumu KAWASHIMA

IPC: H01L25/16 ,  H01L23/15

Abstract: A high-definition display apparatus with a large diagonal size is provided. The display apparatus includes a first layer and a second layer positioned above the first layer. The first layer includes a substrate and a plurality of circuit regions, and the second layer includes a plurality of display regions. The substrate is a glass substrate. Each of the plurality of circuit regions includes a driver circuit, and the driver circuit includes a transistor including low-temperature polysilicon in a channel formation region. Each of the plurality of display regions includes a display pixel, and the display pixel includes a light-emitting device and a transistor including a metal oxide in a channel formation region. The driver circuit included in one of the plurality of circuit regions has a function of driving the display pixel included in one of the plurality of display region.

公开(公告)号：US20240365572A1

公开(公告)日：2024-10-31

申请号：US18764740

申请日：2024-07-05

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Koji KUSUNOKI ,  Kazunori WATANABE ,  Tomoaki ATSUMI ,  Satoshi YOSHIMOTO

IPC: H10K39/34 ,  G06F3/042 ,  G06V40/13 ,  G09G3/3233 ,  H10K59/131

CPC classification number: H10K39/34 ,  G06F3/042 ,  G06V40/1318 ,  G09G3/3233 ,  H10K59/131 ,  G06F2203/04108 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2354/00 ,  G09G2360/14

Abstract: A semiconductor device having a light sensing function and including a high-resolution display portion is provided. The semiconductor device includes a plurality of pixels, and the pixels each include first and second light-receiving devices, first to fifth transistors, a capacitor, and a first wiring. One electrode of the first light-receiving device is electrically connected to the first wiring, and the other electrode is electrically connected to one of a source and a drain of the first transistor. One electrode of the second light-receiving device is electrically connected to the first wiring, and the other electrode is electrically connected to one of a source and a drain of the second transistor. The other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor, one of a source and a drain of the third transistor, and a gate of the fourth transistor.

公开(公告)号：US20240315038A1

公开(公告)日：2024-09-19

申请号：US18613222

申请日：2024-03-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tomoaki ATSUMI ,  Yuta ENDO

IPC: H10B43/35 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  G11C16/0466 ,  G11C16/0483 ,  H10B43/27 ,  H10B43/40 ,  G11C16/10 ,  G11C16/26

Abstract: A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.