公开(公告)号：US4701884A

公开(公告)日：1987-10-20

申请号：US896257

申请日：1986-08-14

申请人： Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara ,  Kiyoo Itoh ,  Hideo Nakamura ,  Osamu Minato

发明人： Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara ,  Kiyoo Itoh ,  Hideo Nakamura ,  Osamu Minato

IPC分类号： G11C11/56 ,  H01L27/108 ,  G11C13/00

CPC分类号： G11C11/565 ,  H01L27/10805

摘要： A semiconductor memory device is proposed wherein at least an array comprising a plurality of memory cells each having at least one capacity, a select mechanism for specifying the position of each memory cell, data lines connected to said memory cells for transmitting the data and a data writing and a data reading mechanisms are provided. The feature of this device lies in that the voltage generator for serially generating three or more values of the voltage which are different from each other and the means for applying said voltage to said memory cells are provided on the same semiconductor board as the same said memory cells, and as the said reading mechanism the column register is provided which, as said reading mechanism, has the mechanism for deciding the data, transfer gate which is provided between said deciding means and said data line, and the bias charge transfer mechanism which is provided between said transfer gate and said deciding mechanism, and having at least two or more memory elements for temporarily storing said decided data.

摘要翻译： 提出了一种半导体存储器件，其中至少包括多个具有至少一个容量的存储单元的阵列，用于指定每个存储单元的位置的选择机构，连接到所述存储器单元的用于发送数据的数据线和数据 提供写入和数据读取机制。 该装置的特征在于，用于串联产生彼此不同的三个或更多个电压值的电压发生器和用于将所述电压施加到所述存储单元的装置设置在与所述存储器相同的半导体板上 并且作为所述读取机构，列寄存器被提供，其作为所述读取机构具有用于确定数据的机制，所述决定装置和所述数据线之间提供的传送门和作为所述读取机构的偏置电荷传送机构 提供在所述传送门和所述判定机构之间，并且具有用于临时存储所述决定的数据的至少两个或更多个存储器元件。

公开(公告)号：US4672586A

公开(公告)日：1987-06-09

申请号：US617919

申请日：1984-06-06

申请人： Katsuhiro Shimohigashi ,  Masaharu Kubo ,  Katsuki Miyauchi ,  Toshiaki Masuhara ,  Osamu Minato

发明人： Katsuhiro Shimohigashi ,  Masaharu Kubo ,  Katsuki Miyauchi ,  Toshiaki Masuhara ,  Osamu Minato

IPC分类号： G11C11/401 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4074 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C11/406 ,  G11C11/4072 ,  G11C11/4074 ,  G11C5/141

摘要： A semiconductor memory using a dynamic memory device, wherein a battery supplies a power source voltage and a substrate bias voltage when the memory is cut off from an external device, and a refresh control circuit changes in refresh timing of the memory device in accordance with the leakage current of the memory device. The power consumption of the memory can thus be reduced and the data can be kept for an extended period without an external power source.

公开(公告)号：US4841486A

公开(公告)日：1989-06-20

申请号：US946776

申请日：1986-12-29

申请人： Osamu Minato ,  Toshiaki Masuhara ,  Koichiro Ishibashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki

发明人： Osamu Minato ,  Toshiaki Masuhara ,  Koichiro Ishibashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki

IPC分类号： H01L27/11 ,  G11C7/06 ,  G11C11/416 ,  G11C11/419 ,  H01L21/8244 ,  H01L27/10

CPC分类号： G11C11/419 ,  G11C7/062

摘要： A semiconductor memory device having a memory plane defined by a plurality of memory cells, a decoder line for accessing the memory cells, a common data line on which a signal output from an accessed memory cell is collected, and a sense amplifier for amplifying the signal collected on the common data line. The sense amplifier has an amplifying circuit portion which is composed of a pair of common-collector type bipolar transistors supplied with the signal collected on the common data line as a differential input, and a plurality of MOS transistors for converting a change in current into a change in voltage. Each of the MOS transistors has a lightly-doped drain structure.

摘要翻译： 一种具有由多个存储单元限定的存储器平面的半导体存储器件，用于访问存储器单元的解码器线，从所访问的存储单元输出的信号被收集的公共数据线，以及用于放大该信号的读出放大器 在公共数据线上收集。 读出放大器具有放大电路部分，该放大电路部分由一对公共集电极型双极晶体管构成，该一对公共集电极型双极晶体管被提供有作为差分输入的公共数据线上收集的信号，以及多个MOS晶体管，用于将电流变化转换为 电压变化。 每个MOS晶体管具有轻掺杂漏极结构。

公开(公告)号：US4609835A

公开(公告)日：1986-09-02

申请号：US471130

申请日：1983-03-01

申请人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki

发明人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki

IPC分类号： G11C11/412 ,  H01L27/06 ,  H01L27/085 ,  H01L27/11 ,  G11C11/40 ,  H01L27/04 ,  H01L29/78 ,  H03K19/094

CPC分类号： H01L27/0688 ,  G11C11/412 ,  H01L27/085 ,  H01L27/1104 ,  H01L27/1112

摘要： Disclosed is a semiconductor integrated circuit which comprises an n-type silicon substrate, a p-type well region having an opening at a part thereof, which is formed on the surface portion of the substrate, an MOS transistor formed in the p-type region and a resistance layer extended from the drain region of the MOS transistor to the opening of the p-type well region through a insulating film formed on the surface of the substrate, in which the drain region of the MOS transistor is electrically connected to the silicon substrate through the resistance layer so that a current is supplied to the MOS transistor.

摘要翻译： 公开了一种半导体集成电路，其包括n型硅衬底，形成在衬底的表面部分上的具有开口的p型阱区，形成在p型区域中的MOS晶体管 以及电阻层，其通过形成在所述衬底的表面上的绝缘膜从所述MOS晶体管的漏极区延伸到所述p型阱区的开口，其中所述MOS晶体管的漏极区域与所述硅 衬底通过电阻层，以便向MOS晶体管提供电流。

公开(公告)号：US4792841A

公开(公告)日：1988-12-20

申请号：US634037

申请日：1984-07-24

申请人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

发明人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11 ,  H01L29/04

CPC分类号： H01L27/1112 ,  H01L21/28525 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/522 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/903

摘要： Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after the polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

摘要翻译： 公开了包括多个硅栅型MOSFET的MOSIC，其中在与多晶硅栅极同时形成多晶硅布线之后，与源极和漏极区域接触的电极由多晶硅制成，以便连接到多晶硅 从而防止源极和漏极区域的浅的pn结被触点破坏并提供与一个硅芯片的高度集成。

公开(公告)号：US4377819A

公开(公告)日：1983-03-22

申请号：US032017

申请日：1979-04-20

申请人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki ,  Hisao Katto ,  Norikazu Hashimoto ,  Shin-ichi Muramatsu ,  Akihiro Tomozawa

发明人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki ,  Hisao Katto ,  Norikazu Hashimoto ,  Shin-ichi Muramatsu ,  Akihiro Tomozawa

IPC分类号： G11C11/412 ,  H01L21/02 ,  H01L21/318 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L27/11 ,  H01L29/06 ,  H01L29/40 ,  H01L29/41 ,  H01L29/04

CPC分类号： H01L29/402 ,  H01L21/3185 ,  H01L27/0605 ,  H01L27/1112 ,  H01L28/20 ,  H01L29/41

摘要： A semiconductor device including at least a resistance element formed of polycrystalline silicon having a high resistivity. An electrode is provided on the high resistance polycrystalline silicon region with a silicon dioxide film and a silicon nitride film being interposed therebetween. The electrode is coupled to the ground potential. In this manner, high stability is obtained in the behavior of the resistance element inasmuch as the formation of a parasitic MOS device under said high resistance region is suppressed, and the threshold voltage of any such MOS device is made raised.

摘要翻译： 一种半导体器件，至少包括由具有高电阻率的多晶硅形成的电阻元件。 在具有二氧化硅膜的高电阻多晶硅区域上设置电极，并且在其间插入有氮化硅膜。 电极与地电位耦合。 以这种方式，由于抑制了在所述高电阻区域下的寄生MOS器件的形成，所以电阻元件的性能得到了很高的稳定性，并且提高了任何这种MOS器件的阈值电压。

公开(公告)号：US5028975A

公开(公告)日：1991-07-02

申请号：US527641

申请日：1990-05-23

申请人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

发明人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11

CPC分类号： H01L27/1112 ,  H01L21/28525 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/522 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/903

摘要： Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, the electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

公开(公告)号：US4492974A

公开(公告)日：1985-01-08

申请号：US350589

申请日：1982-02-22

申请人： Isao Yoshida ,  Takeaki Okabe ,  Mineo Katsueda ,  Minoru Nagata ,  Toshiaki Masuhara ,  Kazutoshi Ashikawa ,  Hideaki Kato ,  Mitsuo Ito ,  Shigeo Ohtaka ,  Osamu Minato ,  Yoshio Sakai

发明人： Isao Yoshida ,  Takeaki Okabe ,  Mineo Katsueda ,  Minoru Nagata ,  Toshiaki Masuhara ,  Kazutoshi Ashikawa ,  Hideaki Kato ,  Mitsuo Ito ,  Shigeo Ohtaka ,  Osamu Minato ,  Yoshio Sakai

IPC分类号： H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/78 ,  H01L29/861 ,  H01L29/90 ,  H02H3/20

CPC分类号： H01L29/7811 ,  H01L27/0255 ,  H01L27/0688 ,  H01L29/7808 ,  H01L29/861 ,  H01L2924/0002

摘要： A semiconductor integrated circuit device is provided to include a vertical type MOSFET and a gate protection element for the MOSFET. The vertical type MOSFET is made up of a silicon layer of n-type conductivity formed on an n.sup.+ -type silicon substrate, a base region of p-type conductivity formed in the surface of the silicon layer of n-type conductivity, an n.sup.+ -type source region provided in the base region, and a gate electrode formed on a portion of the base region through a gate insulating film. The silicon substrate serves as the drain. The gate protection element is formed of a polycrystalline silicon layer which is provided on the base region through an insulating film and includes at least one pn junction. By virtue of forming the gate protection element over the base region rather than directly over the substrate, a more stable operation is achieved.

摘要翻译： 提供半导体集成电路器件以包括用于MOSFET的垂直型MOSFET和栅极保护元件。 垂直型MOSFET由n +型硅衬底上形成的n型导电硅层，n型导电性硅层表面形成的p型导电基极区，n +型硅衬底， 设置在基极区域中的源极区，以及通过栅极绝缘膜形成在基极区域的一部分上的栅电极。 硅衬底用作漏极。 栅极保护元件由多晶硅层形成，该多晶硅层通过绝缘膜设置在基极区上并且包括至少一个pn结。 通过在基极区域而不是直接在衬底上形成栅极保护元件，实现更稳定的操作。

公开(公告)号：US4261004A

公开(公告)日：1981-04-07

申请号：US929959

申请日：1978-08-01

申请人： Toshiaki Masuhara ,  Osamu Minato ,  Yoshio Sakai ,  Toshio Sasaki ,  Masaharu Kubo ,  Kotaro Nishimura ,  Tokumasa Yasui

发明人： Toshiaki Masuhara ,  Osamu Minato ,  Yoshio Sakai ,  Toshio Sasaki ,  Masaharu Kubo ,  Kotaro Nishimura ,  Tokumasa Yasui

IPC分类号： H03F1/52 ,  H01L21/02 ,  H01L21/822 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/78 ,  H03F1/42

CPC分类号： H01L28/20 ,  H01L27/0251 ,  H01L27/0288

摘要： On the surface of an insulating film formed on the surface of a semiconductor substrate on which an MOS type semiconductor device to be protected is formed, there are formed a first polycrystal silicon member having input and output terminals and a resistivity lower than 1 K.OMEGA./.quadrature. and a second polycrystalline silicon member having a resistivity lower than 1 K.OMEGA./.quadrature. and being maintained at a fixed potential. This second polycrystalline silicon member faces at least a part of the first silicon member with polycrystalline silicon of a resistivity higher than 100 K.OMEGA./.quadrature. interposed therebetween. The input terminal of the first polycrystalline silicon member is connected to an input pad of the MOS type semiconductor device to be protected and the output terminal of the first polycrystalline silicon member is connected to an input gate of the semiconductor device to be protected. The input gate of the semiconductor device is protected by utilizing the punch-through effect in the interior of the polycrystalline silicon having a resistivity higher than 100 K.OMEGA./.quadrature..

摘要翻译： 在形成有要形成有待保护的MOS型半导体器件的半导体衬底的表面上的绝缘膜的表面上形成有具有输入和输出端子的电阻率低于1KΩ的第一多晶硅元件， 并且具有电阻率低于1KΩ/□并且保持在固定电位的第二多晶硅部件。 该第二多晶硅部件面对第一硅部件的至少一部分，其中多晶硅的电阻率高于100KΩ，并插入其间。 第一多晶硅部件的输入端子连接到要被保护的MOS型半导体器件的输入焊盘，并且第一多晶硅部件的输出端子连接到待保护的半导体器件的输入栅极。 半导体器件的输入栅极通过利用电阻率高于100KΩ/□的多晶硅的内部的穿透效应来保护。

公开(公告)号：US5619055A

公开(公告)日：1997-04-08

申请号：US429882

申请日：1995-04-27

申请人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

发明人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/76

CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

摘要： A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source region and gate electrode of each load MISFET thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error. The overlapping relationship for effecting the large capacitor element across the source and gate of the respective load MISFETs is provided by an ion implanting scheme of a p-type impurity into the semiconductor strip. A separate mask for ion-implantation for the formation of the source region of the load MISFET is added followed by the addition of the gate electrode thereof in a manner so as to have a widely overlapping relationship with that of the source region.

摘要翻译： 公开了采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFET之上。 存储单元的每个负载MISFET由诸如多晶硅膜条的半导体条形成的源极，漏极和沟道区域以及由不同于导电膜的驱动MISFET组成的栅电极构成。 在具有这种堆叠布置的存储器单元中，每个负载MISFET的源极区域和栅电极被图案化以具有彼此广泛重叠的关系，以形成电容器元件，使得与每个负载MISFET相关联的总体电容的增加 存储单元存储节点被实现，从而减少软错误的发生。 通过p型杂质离子注入到半导体条中的方式来提供跨越各个负载MISFET的源极和栅极的大电容器元件的重叠关系。 添加用于形成负载MISFET的源极区域的离子注入的单独的掩模，然后以与源极区域具有广泛重叠的关系的方式添加其栅电极。