公开(公告)号：US09502335B2

公开(公告)日：2016-11-22

申请号：US14487548

申请日：2014-09-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Hsien-Wen Chen ,  Hong-Da Chang ,  Mao-Hua Yeh

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/49 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15323 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00

Abstract: A package structure is provided, which includes: a chip carrier having a plurality of conductive connection portions; at least an electronic element disposed on the chip carrier; a plurality of conductive wires erectly positioned on the conductive connection portions, respectively; an encapsulant formed on the chip carrier for encapsulating the conductive wires and the electronic element, wherein one ends of the conductive wires are exposed from the encapsulant; and a circuit layer formed on the encapsulant and electrically connected to exposed ends of the conductive wires. According to the present invention, the conductive wires serve as an interconnection structure. Since the wire diameter of the conductive wires is small and the pitch between the conductive wires can be minimized, the present invention reduces the size of the chip carrier and meets the miniaturization requirement.

Abstract translation: 提供一种封装结构，其包括：具有多个导电连接部分的芯片载体; 至少设置在所述芯片载体上的电子元件; 多个导线分别竖立设置在导电连接部分上; 形成在所述芯片载体上用于封装所述导线和所述电子元件的密封剂，其中所述导线的一端从所述密封剂露出; 以及形成在密封剂上并电连接到导线的露出端的电路层。 根据本发明，导线用作互连结构。 由于导线的线径小，导线之间的间距可以最小化，因此本发明可以减小芯片载体的尺寸并满足小型化要求。

公开(公告)号：US20220005786A1

公开(公告)日：2022-01-06

申请号：US17481610

申请日：2021-09-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Yuan Wang ,  Feng Kao ,  Mao-Hua Yeh

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/16 ,  H01L25/00 ,  H01L23/31

Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.

公开(公告)号：US11152331B2

公开(公告)日：2021-10-19

申请号：US16673078

申请日：2019-11-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Yuan Wang ,  Feng Kao ,  Mao-Hua Yeh

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/16 ,  H01L25/00 ,  H01L23/31

Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.

公开(公告)号：US10679914B2

公开(公告)日：2020-06-09

申请号：US15635446

申请日：2017-06-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Cheng-Yi Chen ,  Chun-Hung Lu ,  Mao-Hua Yeh

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/16 ,  H01L21/78 ,  H01L21/56

Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.

公开(公告)号：US20180254232A1

公开(公告)日：2018-09-06

申请号：US15635446

申请日：2017-06-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Cheng-Yi Chen ,  Chun-Hung Lu ,  Mao-Hua Yeh

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.

公开(公告)号：US09831191B2

公开(公告)日：2017-11-28

申请号：US15149576

申请日：2016-05-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Mao-Hua Yeh ,  Hung-Yuan Li ,  Shih-Liang Peng ,  Chang-Lun Lu

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2021/60022 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor substrate is provided, including a substrate body, a plurality of conductive through holes penetrating the substrate body, and at least one pillar disposed in the substrate body with the at least one pillar being free from penetrating the substrate body. When the semiconductor substrate is heated, the at least one pillar adjusts the expansion of upper and lower sides of the substrate body. Therefore, the upper and lower sides of the substrate body have substantially the same thermal deformation, and the substrate body is prevented from warpage.

公开(公告)号：US11747382B2

公开(公告)日：2023-09-05

申请号：US16723233

申请日：2019-12-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Bo-Siang Fang ,  Kuang-Sheng Wang ,  Hsinjou Lin ,  Shao-Meng Sim ,  Mao-Hua Yeh

IPC: G01R29/10 ,  H04B17/29

CPC classification number: G01R29/105 ,  H04B17/29

Abstract: Testing equipment is used in an antenna testing process, and includes a testing head having a perforation, and a testing device having a cylinder. The cylinder is disposed in the perforation to act as a cavity for the antenna testing process. Therefore, only the cylinder needs to be replaced when the antenna testing process is performed on different devices under test, with the whole testing head intact.

公开(公告)号：US11081415B2

公开(公告)日：2021-08-03

申请号：US16862024

申请日：2020-04-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Cheng-Yi Chen ,  Chun-Hung Lu ,  Mao-Hua Yeh

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/16

Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.

公开(公告)号：US20200258802A1

公开(公告)日：2020-08-13

申请号：US16862024

申请日：2020-04-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Cheng-Yi Chen ,  Chun-Hung Lu ,  Mao-Hua Yeh

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L23/16

Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.

公开(公告)号：US20200235462A1

公开(公告)日：2020-07-23

申请号：US16535022

申请日：2019-08-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Jung Tsai ,  Mao-Hua Yeh ,  Chih-Hsien Chiu ,  Ying-Chou Tsai ,  Chun-Chi Ke

IPC: H01Q1/22 ,  H01Q1/36 ,  H01L23/31 ,  H01L23/498 ,  H01L23/66 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: An electronic package and a method for fabricating the same are provided. An antenna frame, a first electronic component, and a second electronic component electrically connected to the antenna frame are disposed on a lower side of a carrying structure. An antenna structure is disposed on an upper side of the carrying structure and is electrically connected to the first electronic component. Therefore, two different types of antennas are integrated into an identical electronic package. Such the electronic package bonded to a circuit can transmit signals with two different wavelengths, even if the electronic package does not have any area increased.