公开(公告)号：US20180151487A1

公开(公告)日：2018-05-31

申请号：US15361401

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/367 ,  H01L23/373 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/288 ,  H01L21/285 ,  H01L21/324 ,  H01L21/3105

CPC classification number: H01L23/528 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76895 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/53209 ,  H01L23/53276

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

公开(公告)号：US20160293834A1

公开(公告)日：2016-10-06

申请号：US14676233

申请日：2015-04-01

Applicant: Texas Instruments Incorporated

Inventor： Arup Polley ,  Archana Venugopal ,  Robert Reid Doering ,  Luigi Colombo

IPC: H01L43/10 ,  G01R33/07 ,  H01L43/06

CPC classification number: H01L43/10 ,  G01R33/07 ,  H01L43/065

Abstract: Described examples include graphene Hall sensors, magnetic sensor systems and methods for sensing a magnetic field using an adjustable gate voltage to adapt the Hall sensor magnetic field sensitivity according to a control input for environmental or process compensation and/or real-time adaptation for balancing power consumption and minimum detectable field performance. The graphene Hall sensor gate voltage can be modulated and the sensor output signal can be demodulated to combat flicker or other low frequency noise. Also, graphene Hall sensors can be provided with capacitive coupled contacts for reliable low impedance AC coupling to instrumentation amplifiers or other circuits using integral capacitance.

Abstract translation: 所描述的实例包括石墨烯霍尔传感器，磁传感器系统和用于使用可调节栅极电压感测磁场的方法，以根据用于环境或过程补偿的控制输入和/或用于平衡功率的实时适应来适应霍尔传感器的磁场灵敏度 消耗和最小可检测现场性能。 可以对石墨烯霍尔传感器门电压进行调制，并且传感器输出信号可被解调，以防止闪烁或其他低频噪声。 此外，石墨烯霍尔传感器可以提供电容耦合触点，用于可靠的低阻抗交流耦合到仪表放大器或使用积分电容的其他电路。

公开(公告)号：US09397023B2

公开(公告)日：2016-07-19

申请号：US14499216

申请日：2014-09-28

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Marie Denison ,  Luigi Colombo ,  Sameer Pendharkar

IPC: H01L23/34 ,  H01L23/373 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/48 ,  H01L21/02

CPC classification number: H01L23/3672 ,  H01L21/02491 ,  H01L21/02527 ,  H01L21/02606 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/76877 ,  H01L23/373 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53276 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/48463 ,  H01L2224/49107 ,  H01L2924/00

Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Abstract translation: 微电子器件包括在部件的电极上的散热层和散热器层上的金属互连。 散热器层设置在半导体器件的衬底的顶表面之上。 散热器层为100纳米至3微米厚，面内热导率至少为150瓦特/米-2°K，电阻率小于100微欧姆厘米。

公开(公告)号：US20160093551A1

公开(公告)日：2016-03-31

申请号：US14499216

申请日：2014-09-28

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Marie Denison ,  Luigi Colombo ,  Sameer Pendharkar

IPC: H01L23/373 ,  H01L23/522 ,  H01L21/02 ,  H01L21/768 ,  H01L21/48 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/3672 ,  H01L21/02491 ,  H01L21/02527 ,  H01L21/02606 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/76877 ,  H01L23/373 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53276 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/48463 ,  H01L2224/49107 ,  H01L2924/00

Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Abstract translation: 微电子器件包括在部件的电极上的散热层和散热器层上的金属互连。 散热器层设置在半导体器件的衬底的顶表面上方。 散热器层为100纳米至3微米厚，面内热导率至少为150瓦特/米-2°K，电阻率小于100微欧姆厘米。

公开(公告)号：US11938715B2

公开(公告)日：2024-03-26

申请号：US16229668

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Luigi Colombo ,  Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal

IPC: B32B9/00 ,  B32B9/04 ,  C01B32/184 ,  C01B32/19 ,  C23C18/32 ,  C23C18/38 ,  H01M50/00 ,  B82Y30/00

CPC classification number: B32B9/007 ,  B32B9/041 ,  B32B9/045 ,  C01B32/184 ,  C01B32/19 ,  C23C18/32 ,  C23C18/38 ,  H01M50/00 ,  B32B2305/38 ,  B32B2457/14 ,  B82Y30/00 ,  C01P2002/20 ,  Y10T428/30

Abstract: A microstructure comprises a plurality of interconnected units wherein the units are formed of graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice.

公开(公告)号：US11004680B2

公开(公告)日：2021-05-11

申请号：US15361403

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/373 ,  H01L21/56 ,  H01L23/433 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: A packaged electronic device includes an integrated circuit and an electrically non-conductive encapsulation material in contact with the integrated circuit. A thermal conduit extends from an exterior of the package, through the encapsulation material, to the integrated circuit. The thermal conduit has a thermal conductivity higher than the encapsulation material contacting the thermal conduit. The thermal conduit includes a cohered nanoparticle film. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US10923567B2

公开(公告)日：2021-02-16

申请号：US16792379

申请日：2020-02-17

Applicant: Texas Instruments Incorporated

Inventor： Luigi Colombo ,  Archana Venugopal

IPC: H01L29/16 ,  H01L29/786 ,  H01L51/00 ,  H01L51/05 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/417 ,  H01L21/02 ,  H01L29/51

Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function

公开(公告)号：US10804201B2

公开(公告)日：2020-10-13

申请号：US16236101

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Nazila Dadvand ,  Luigi Colombo

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  C01B32/184 ,  H01L23/522

Abstract: A structure for a semiconductor device includes a dielectric layer and a metal layer. The structure also includes a plurality of unit cells. Each unit cell is formed of interconnected segments. The plurality of unit cells forms a lattice. The lattice is between the dielectric layer and the metal layer.

公开(公告)号：US20200211849A1

公开(公告)日：2020-07-02

申请号：US16810891

申请日：2020-03-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Luigi Colombo ,  Archana Venugopal

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/786 ,  H01L29/45 ,  H01L51/05 ,  H01L51/00

Abstract: A method, e.g. of forming an electronic device, includes forming a carbon-doped metal layer over a substrate. The carbon-doped metal layer is heated and cooled such that a first graphene layer is formed on a top surface of the carbon-doped metal layer, and a second graphene layer is formed between the carbon-doped metal layer and the substrate. A portion of the first graphene layer is removed and a portion of the carbon-doped metal layer is removed, thereby forming first and second spaced-apart contact layers on the second graphene layer.

公开(公告)号：US10593763B2

公开(公告)日：2020-03-17

申请号：US16211800

申请日：2018-12-06

Applicant: Texas Instruments Incorporated

Inventor： Luigi Colombo ,  Archana Venugopal

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/786 ,  H01L51/00 ,  H01L51/05 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/417 ,  H01L21/02 ,  H01L29/51

Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function