公开(公告)号：US4881103A

公开(公告)日：1989-11-14

申请号：US114867

申请日：1987-10-30

申请人： Yutaka Seto ,  Shigehiro Suzuki ,  Tomohiro Suzuki ,  Atsushi Fujita ,  Akira Tai ,  Masahiro Yoshino

发明人： Yutaka Seto ,  Shigehiro Suzuki ,  Tomohiro Suzuki ,  Atsushi Fujita ,  Akira Tai ,  Masahiro Yoshino

IPC分类号： G03G15/08 ,  G03G15/09

CPC分类号： G03G15/09 ,  G03G15/0822 ,  G03G15/0856 ,  G03G15/0858 ,  G03G15/0889

摘要： This invention discloses a developing apparatus wherein a brush of a developing agent is formed on a developing sleeve by a magnetic field of a permanent magnet disposed inside the developing sleeve, and at least the developing sleeve is rotated while the brush is kept in contact with a photosensitive body, thereby developing an electrostatic latent image formed on the photosensitive body. In this apparatus, an agitating member having magnetic ring portions which abut against the developing sleeve and an agitating portion for agitating the developing agent is pivotally disposed in a developing vessel to be parallel to the developing sleeve, and a rotation detecting unit for outputting a signal corresponding to a rotational speed of the agitating member and a residual amount detecting unit for detecting a residual amount of the developing agent in the developing vessel in accordance with an output from the rotation detecting unit are provided.

摘要翻译： 本发明公开了一种显影装置，其中通过设置在显影套筒内部的永磁体的磁场在显影套筒上形成显影剂刷，并且至少显影套筒旋转，同时刷子保持与一个 感光体，从而显影形成在感光体上的静电潜像。 在该装置中，具有与显影套筒抵接的磁环部分的搅拌部件和用于搅拌显影剂的搅拌部分可转动地设置在显影容器中以与显影套筒平行;旋转检测单元，用于输出信号 相应于搅拌构件的旋转速度和残留量检测单元，用于根据旋转检测单元的输出检测显影槽中的显影剂残留量。

公开(公告)号：US20110207264A1

公开(公告)日：2011-08-25

申请号：US12905395

申请日：2010-10-15

申请人： Manabu TOMISAKA ,  Akira Tai ,  Kazuo Akamatsu ,  Yutaka Fukuda ,  Yoshiko Fukuda ,  Yuji Fukuda ,  Mika Ootsuki ,  Mayu Fukuda

发明人： Manabu TOMISAKA ,  Akira Tai ,  Kazuo Akamatsu ,  Yutaka Fukuda ,  Yoshiko Fukuda ,  Yuji Fukuda ,  Mika Ootsuki ,  Mayu Fukuda

IPC分类号： H01L21/56

CPC分类号： H01L21/304 ,  H01L29/66333 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device includes cutting a part of a resin insulating layer formed on a surface of a semiconductor substrate with a cutting tool. The cutting the part of the resin insulating layer includes cutting a portion of the resin insulating layer that has a surface on which a metal layer is disposed. The cutting the portion of the resin insulating layer is performed in such a manner that, in a stress distribution inside the resin insulating layer along an edge portion of the cutting tool and a peripheral portion of the edge portion, a width at 90% of a maximum value is not more than 1.3 μm.

摘要翻译： 半导体器件的制造方法包括：利用切削工具切断形成在半导体基板的表面上的树脂绝缘层的一部分。 切割树脂绝缘层的一部分包括切割具有设置有金属层的表面的树脂绝缘层的一部分。 切割树脂绝缘层的部分是这样一种方式进行的：在树脂绝缘层沿着切削工具的边缘部分和边缘部分的周边部分的应力分布中，90％的宽度 最大值不大于1.3μm。

公开(公告)号：US07105910B2

公开(公告)日：2006-09-12

申请号：US10994294

申请日：2004-11-23

申请人： Seiichiro Ishio ,  Akira Tai

发明人： Seiichiro Ishio ,  Akira Tai

IPC分类号： H01L29/00

CPC分类号： H01L21/743 ,  H01L21/76275 ,  H01L21/76286 ,  H01L21/84 ,  H01L23/585 ,  H01L24/81 ,  H01L27/1203 ,  H01L29/8605 ,  H01L29/945 ,  H01L2224/81801

摘要： A semiconductor device includes: a semiconductor substrate including a first semiconductor layer, an insulation layer and a second semiconductor layer, which are laminated in this order; a trench penetrating both of the second semiconductor layer and the insulation layer and reaching the first semiconductor layer; and a third semiconductor layer. The trench has a ring shape on a principal surface of the substrate so that a part of the second semiconductor layer and a part of the insulation layer are surrounded with the trench. The third semiconductor layer is disposed in the trench through a first insulation film disposed on a sidewall of the trench so that the third semiconductor layer contacts the first semiconductor layer at a bottom of the trench.

摘要翻译： 半导体器件包括：依次层叠的包括第一半导体层，绝缘层和第二半导体层的半导体衬底; 穿过所述第二半导体层和所述绝缘层的沟槽并到达所述第一半导体层的沟槽; 和第三半导体层。 沟槽在基板的主表面上具有环形形状，使得第二半导体层的一部分和绝缘层的一部分被沟槽包围。 第三半导体层通过布置在沟槽的侧壁上的第一绝缘膜设置在沟槽中，使得第三半导体层在沟槽的底部接触第一半导体层。

公开(公告)号：US20060071284A1

公开(公告)日：2006-04-06

申请号：US11239088

申请日：2005-09-30

申请人： Akira Tai ,  Yoshiaki Nakayama

发明人： Akira Tai ,  Yoshiaki Nakayama

IPC分类号： H01L29/76

CPC分类号： H01L22/34 ,  H01L21/02129 ,  H01L21/31612 ,  H01L21/31625 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first insulation film, a second insulation film, a thin film resistor interposed between the insulation films. A predetermined voltage is applied to the thin film resistor so that a current flows through the thin film resistor. When a crack occurs in the insulation films, the thin film resistor is partially destroyed and the resistance of the thin film resistor changes. The crack is detected by measuring the change in resistance of the thin film resistor based on the predetermined voltage and the current flowing through the thin film resistor. Therefore, a crack inspection can be conducted without destruction of the device.

摘要翻译： 半导体器件包括第一绝缘膜，第二绝缘膜，介于绝缘膜之间的薄膜电阻器。 向薄膜电阻器施加预定电压，使得电流流过薄膜电阻器。 当绝缘膜发生裂纹时，薄膜电阻部分被破坏，薄膜电阻的电阻变化。 通过基于预定电压和流过薄膜电阻器的电流测量薄膜电阻器的电阻变化来检测裂纹。 因此，可以在不破坏装置的情况下进行裂纹检查。

公开(公告)号：US20050189617A1

公开(公告)日：2005-09-01

申请号：US11065150

申请日：2005-02-25

申请人： Shoji Mizuno ,  Akira Tai ,  Takashi Nakano

发明人： Shoji Mizuno ,  Akira Tai ,  Takashi Nakano

IPC分类号： H01L21/331 ,  H01L27/082 ,  H01L29/10 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735

CPC分类号： H01L29/735 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/732

摘要： A bipolar transistor includes: a base having a first conductive type; an emitter having a second conductive type; a collector having the second conductive type; and a plurality of interceptors for intercepting a carrier path of a current in the base. The carrier path is disposed between the emitter and the collector through the base. Each interceptor is disposed on a shortest distance line of the carrier path in the base between the emitter and the collector. The carrier path is lengthened substantially without increasing the size of the transistor so that the transistor has a high withstand voltage. Further, the carrier path bypasses the interceptors so that the transport efficiency is not reduced substantially.

摘要翻译： 双极晶体管包括：具有第一导电类型的基极; 具有第二导电类型的发射极; 具有第二导电类型的集电器; 以及用于截取基座中的电流的载波路径的多个拦截器。 载体路径通过基底设置在发射极和集电极之间。 每个拦截器设置在发射器和收集器之间的基座中的载体路径的最短距离线上。 载体路径基本上延长而不增加晶体管的尺寸，使得晶体管具有高的耐受电压。 此外，载体路径绕过拦截器，使得传输效率没有显着降低。

公开(公告)号：US08263490B2

公开(公告)日：2012-09-11

申请号：US12923576

申请日：2010-09-28

申请人： Manabu Tomisaka ,  Hidetoshi Katou ,  Yutaka Fukuda ,  Akira Tai ,  Kazuo Akamatsu ,  Yoshiko Fukuda ,  Yuji Fukuda ,  Mika Ootsuki

发明人： Manabu Tomisaka ,  Hidetoshi Katou ,  Yutaka Fukuda ,  Akira Tai ,  Kazuo Akamatsu ,  Yoshiko Fukuda ,  Yuji Fukuda ,  Mika Ootsuki

IPC分类号： H01L21/44

CPC分类号： G01B11/06 ,  G01B11/306 ,  H01L21/32115 ,  H01L21/7684 ,  H01L22/12 ,  H01L22/20 ,  H01L24/27 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  Y10T29/52 ,  H01L2924/01014 ,  H01L2924/00

摘要： A formation method of a metallic electrode of a semiconductor device is disclosed. The method includes: acquiring data about surface shape of a surface part of a semiconductor substrate; and causing a deformation device to deform the semiconductor substrate based on the data so that a distance between a cutting plane and the surface part falls within a required accuracy in cutting amount. In deforming the semiconductor substrate, multiple actuators are used as the deformation device. A pitch of the multiple actuators is set to a value that is greater than one-half of wavelength of spatial frequency of a thickness distribution of the semiconductor substrate and that is less than or equal to the wavelength.

摘要翻译： 公开了半导体器件的金属电极的形成方法。 该方法包括：获取关于半导体衬底的表面部分的表面形状的数据; 并且使变形装置基于数据使半导体衬底变形，使得切割平面和表面部分之间的距离落入所需切割量的精度。 在使半导体基板变形时，使用多个致动器作为变形装置。 多个致动器的间距被设定为大于半导体衬底的厚度分布的空间频率的波长的一半的值，小于或等于该波长的值。

公开(公告)号：US20110042741A1

公开(公告)日：2011-02-24

申请号：US12805733

申请日：2010-08-17

申请人： Daisuke Fukuoka ,  Takanori Teshima ,  Kuniaki Mamitsu ,  Ken Sakamoto ,  Manabu Tomisaka ,  Tetsuo Fujii ,  Akira Tai ,  Kazuo Akamatsu ,  Masayoshi Nishihata

发明人： Daisuke Fukuoka ,  Takanori Teshima ,  Kuniaki Mamitsu ,  Ken Sakamoto ,  Manabu Tomisaka ,  Tetsuo Fujii ,  Akira Tai ,  Kazuo Akamatsu ,  Masayoshi Nishihata

IPC分类号： H01L29/772 ,  H01L23/498

CPC分类号： H01L23/3192 ,  H01L23/4334 ,  H01L23/492 ,  H01L24/01 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/16 ,  H01L2224/48491 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13055 ,  H01L2924/3512 ,  H01L2924/00

摘要： A semiconductor device includes a first protection film for covering a first metal wiring. A second protection film is disposed on the first protection film, which is covered with a solder layer. Even if a crack is generated in the second protection film before the solder layer is formed on the second protection film, the crack is restricted from proceeding into the first protection film.

摘要翻译： 半导体器件包括用于覆盖第一金属布线的第一保护膜。 第一保护膜设置在第一保护膜上，该第一保护膜被焊料层覆盖。 即使在第二保护膜上形成焊料层之前，在第二保护膜中产生裂纹，限制裂纹进入第一保护膜。

公开(公告)号：US07796442B2

公开(公告)日：2010-09-14

申请号：US12078446

申请日：2008-03-31

申请人： Mitsutaka Katada ,  Yukiaki Yogo ,  Akira Tai ,  Yukihiko Watanabe

发明人： Mitsutaka Katada ,  Yukiaki Yogo ,  Akira Tai ,  Yukihiko Watanabe

IPC分类号： G11C16/04

CPC分类号： H01L29/4983 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate having a source, a drain, and a channel region between the source and the drain. The channel region has a first end portion near the drain, a second end portion near the source, and a middle portion between the first and second end portions. The first and second end portions having approximately same width. The memory device is electrically erased by using a hot carrier generated in the first end portion due to avalanche breakdown. The channel region includes a first channel extending from the drain and a second channel adjacent to the first channel. An impurity concentration of the second channel is higher than that of the first channel. An interface between the first and second channels is located in the middle portion between the first and second end portions.

摘要翻译： 非易失性半导体存储器件包括在源极和漏极之间具有源极，漏极和沟道区域的半导体衬底。 沟道区域具有靠近漏极的第一端部，靠近源极的第二端部，以及第一和第二端部之间的中间部分。 第一和第二端部具有大致相同的宽度。 通过使用由于雪崩击穿而在第一端部中产生的热载体来电存储器件。 沟道区域包括从漏极延伸的第一通道和邻近第一通道的第二通道。 第二通道的杂质浓度高于第一通道的杂质浓度。 第一和第二通道之间的界面位于第一和第二端部之间的中间部分。

公开(公告)号：US20050110116A1

公开(公告)日：2005-05-26

申请号：US10994294

申请日：2004-11-23

申请人： Seiichiro Ishio ,  Akira Tai

发明人： Seiichiro Ishio ,  Akira Tai

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/60 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L23/48 ,  H01L23/58 ,  H01L27/12 ,  H01L29/8605 ,  H01L29/861 ,  H01L29/94 ,  H01L29/74

CPC分类号： H01L21/743 ,  H01L21/76275 ,  H01L21/76286 ,  H01L21/84 ,  H01L23/585 ,  H01L24/81 ,  H01L27/1203 ,  H01L29/8605 ,  H01L29/945 ,  H01L2224/81801

摘要： A semiconductor device includes: a semiconductor substrate including a first semiconductor layer, an insulation layer and a second semiconductor layer, which are laminated in this order; a trench penetrating both of the second semiconductor layer and the insulation layer and reaching the first semiconductor layer; and a third semiconductor layer. The trench has a ring shape on a principal surface of the substrate so that a part of the second semiconductor layer and a part of the insulation layer are surrounded with the trench. The third semiconductor layer is disposed in the trench through a first insulation film disposed on a sidewall of the trench so that the third semiconductor layer contacts the first semiconductor layer at a bottom of the trench.

摘要翻译： 半导体器件包括：依次层叠的包括第一半导体层，绝缘层和第二半导体层的半导体衬底; 穿过所述第二半导体层和所述绝缘层的沟槽并到达所述第一半导体层的沟槽; 和第三半导体层。 沟槽在基板的主表面上具有环形形状，使得第二半导体层的一部分和绝缘层的一部分被沟槽包围。 第三半导体层通过布置在沟槽的侧壁上的第一绝缘膜设置在沟槽中，使得第三半导体层在沟槽的底部接触第一半导体层。

公开(公告)号：US06818942B2

公开(公告)日：2004-11-16

申请号：US10330167

申请日：2002-12-30

申请人： Akira Tai ,  Shoji Mizuno

发明人： Akira Tai ,  Shoji Mizuno

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11558

摘要： In a non-volatile semiconductor storage device, a barrier layer is disposed, via an interlayer isolating film, in an area surrounding a floating gate, including an area adjoining a connecting part of the floating gate, without covering the floating gate. The edge of the barrier layer is, in an overhead view relative to the surface of the semiconductor substrate, disposed at a space of 2 &mgr;m apart from the edge of the floating gate.

摘要翻译： 在非易失性半导体存储装置中，阻挡层通过层间绝缘膜设置在包围与浮动栅极的连接部分相邻的区域的浮动栅极周围的区域中，而不覆盖浮置栅极。 在相对于半导体衬底的表面的俯视图中，阻挡层的边缘设置在与浮动栅极的边缘分开的2μm的空间处。