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    Metallization performance in electronic devices
    11.
    发明申请
    Metallization performance in electronic devices 有权
    电子设备的金属化性能

    公开(公告)号：US20060038294A1

    公开(公告)日：2006-02-23

    申请号：US10919591

    申请日：2004-08-17

    Applicant: John Desko ,  Bailey Jones ,  Sean Lian ,  Simon Molloy ,  Vivian Ryan

    Inventor： John Desko ,  Bailey Jones ,  Sean Lian ,  Simon Molloy ,  Vivian Ryan

    IPC: H01L23/52

    CPC classification number: H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planarities typically of at least 0.02 μm in height and advantageously within 100 μm of another such non-planarity. Such non-planarities, it is contemplated, reduce grain boundary movement in the overlying interconnect with a concomitant reduction in void aggregation.

    Abstract translation: 诸如集成电路的器件的金属互连中发生的诸如电迁移和应力诱发迁移的现象通过使用下面的非平面性被抑制。 因此，互连下面的材料形成为具有通常在高度上通常为至少0.02μm的非平坦度，并且有利地在另一个这样的非平面性的100μm之内。 可以预期的是，这种非平面性减少了上覆互连中的晶界运动，伴随着空隙聚集的降低。

    Semiconductor device having a dummy conductive via and a method of manufacture therefor
    12.
    发明申请
    Semiconductor device having a dummy conductive via and a method of manufacture therefor 有权
    具有虚拟导电通孔的半导体器件及其制造方法

    公开(公告)号：US20050248033A1

    公开(公告)日：2005-11-10

    申请号：US10842139

    申请日：2004-05-10

    Applicant: Vivian Ryan

    Inventor： Vivian Ryan

    IPC: H01L21/768 ,  H01L23/522 ,  H01L29/788

    CPC classification number: H01L21/76838 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one aspect, the present invention provides a semiconductor device having a dielectric layer located over a conductive feature and a conductive via located within the dielectric layer and contacting the conductive feature. The semiconductor device, among other elements, may further include a dummy conductive via located proximate the conductive via and contacting the conductive feature. One of the intents of the dummy conductive via is to attempt to trap vacancies associated with the conductive feature or the conductive via.

    Abstract translation: 本发明提供一种半导体器件及其制造方法以及包括该半导体器件的集成电路。 在一个方面，本发明提供一种半导体器件，其具有位于导电特征之上的电介质层和位于电介质层内并与导电特征接触的导电通孔。 除了其它元件之外，半导体器件还可以包括位于导电通孔附近并接触导电特征的虚拟导电通孔。 虚拟导电通孔的意图之一是尝试捕获与导电特征或导电通孔相关联的空位。

    Methods and apparatus for the detection of damaged regions on dielectric film or other portions of a die
    13.
    发明授权
    Methods and apparatus for the detection of damaged regions on dielectric film or other portions of a die 失效
    用于检测电介质膜或模具的其它部分上的损伤区域的方法和装置

    公开(公告)号：US06919228B2

    公开(公告)日：2005-07-19

    申请号：US10699021

    申请日：2003-10-31

    Applicant: Sean Lian ,  Vivian Ryan ,  Debra Louise Yencho

    Inventor： Sean Lian ,  Vivian Ryan ,  Debra Louise Yencho

    IPC: G01N21/91 ,  H01L21/66 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

    CPC classification number: H01L22/24 ,  G01N21/91 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Techniques for detecting damage on an integrated circuit die using a particle suspension solution are disclosed. The particles of the suspension solution preferentially attach to damaged regions on exposed dielectric films or other portions of the die. For example, one aspect of the invention is a method of detecting damage to a dielectric film used in fabricating a die of an integrated circuit. A particle suspension solution is applied to the die and damaged regions of the dielectric film are identified as areas having an accumulation of particles of the particle suspension solution.

    Abstract translation: 公开了使用颗粒悬浮液检测集成电路管芯上的损坏的技术。 悬浮溶液的颗粒优先附着在暴露的介电膜或模具的其它部分上的损伤区域上。 例如，本发明的一个方面是检测用于制造集成电路的管芯的电介质膜的损坏的方法。 将颗粒悬浮液施加到模具，并且将电介质膜的损伤区域识别为具有颗粒悬浮液的颗粒堆积的区域。

    Integrated circuit having stress migration test structure and method therefor
    14.
    发明授权
    Integrated circuit having stress migration test structure and method therefor 有权
    具有应力迁移试验结构的集成电路及其方法

    公开(公告)号：US06683465B2

    公开(公告)日：2004-01-27

    申请号：US10007417

    申请日：2001-10-31

    Applicant: H. Scott Fetterman ,  Vivian Ryan

    Inventor： H. Scott Fetterman ,  Vivian Ryan

    IPC: G01R3126

    CPC classification number: G01R31/2886 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: A stress migration test structure is provided that can be used to detect stress migration defects in traces or conductors of integrated circuits. The stress migration test structure can be placed between die areas on a wafer, or on a die. On the die, a stress migration test structure can be placed in otherwise unused areas of a die such as between bond pads and the periphery of a die, in a layer beneath bond pads, in a region between the bond pads and the perimeter of standard area for circuit layout, or in regions in more than one level of the integrated circuit. The stress migration test structure may also be placed within the standard area for circuit layout and used, with some additional circuitry, as a stress migration test structure on an integrated circuit once the die is packaged. Obtaining information from the impedance segments of a stress migration test structure can be accomplished employing either a mechanical stepping or an electrical stepping technique.

    Abstract translation: 提供了可用于检测集成电路的迹线或导体中的应力迁移缺陷的应力迁移测试结构。 应力迁移测试结构可以放置在晶片上的模具区域或模具之间。 在模具上，应力迁移测试结构可以放置在管芯的其他未使用的区域中，例如在接合焊盘和管芯的外围之间，在接合焊盘下方的层中，在接合焊盘和标准的周边之间的区域中 电路布局区域，或集成电路多个级别的区域。 应力迁移测试结构也可以放置在用于电路布局的标准区域内，并且使用一些额外的电路作为封装芯片时的集成电路上的应力迁移测试结构。 从应力迁移测试结构的阻抗段获取信息可以采用机械步进或电动步进技术来实现。

    Bond pad design for integrated circuits
    15.
    发明授权
    Bond pad design for integrated circuits 失效
    用于集成电路的焊盘设计

    公开(公告)号：US5986343A

    公开(公告)日：1999-11-16

    申请号：US072369

    申请日：1998-05-04

    Applicant: Sailesh Chittipeddi ,  Vivian Ryan

    Inventor： Sailesh Chittipeddi ,  Vivian Ryan

    IPC: H01L27/04 ,  H01L21/60 ,  H01L21/822 ,  H01L23/485 ,  H01L23/48

    CPC classification number: H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2224/85424 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/1306 ,  H01L2924/14

    Abstract: The present invention provides a bond pad support structure for use in an integrated circuit having a bond pad located thereon. In one embodiment, the bond pad support structure comprises a support layer that is located below the bond pad and that has an opening formed therein. The bond pad support structure further includes a dielectric layer that is located on the conductive layer and that extends at least partially into the opening to form a bond pad support surface over at least a portion of the opening. The first bond pad support layer, in one embodiment, may comprise a conductive metal and the second bond pad support layer may comprise of a dielectric material. The present invention provides a unique bond pad structure wherein an opening within a first bond pad support layer is at least partially filled with a second bond pad support layer. It is believed that the inter-structural cooperation between these two layers provides a graded composite support structure that acts as a differential force transducer to buffer internal and bonding stresses within an integrated circuit.

    Abstract translation: 本发明提供一种用于集成电路中的接合焊盘支撑结构，该集成电路具有位于其上的接合焊盘。 在一个实施例中，接合焊盘支撑结构包括位于接合焊盘下方并且具有形成在其中的开口的支撑层。 接合焊盘支撑结构还包括位于导电层上并且至少部分地延伸到开口中以在开口的至少一部分上形成接合焊盘支撑表面的电介质层。 在一个实施例中，第一接合焊盘支撑层可以包括导电金属，并且第二接合焊盘支撑层可以包括电介质材料。 本发明提供了一种独特的接合焊盘结构，其中第一接合焊盘支撑层内的开口至少部分地被第二接合焊盘支撑层填充。 据信这两层之间的结构间协作提供了一种梯度复合支撑结构，其作为差分力传感器来缓冲集成电路内的内部和结合应力。

    On-Chip Sensor Array for Temperature Management in Integrated Circuits
    19.
    发明申请
    On-Chip Sensor Array for Temperature Management in Integrated Circuits 有权
    用于集成电路温度管理的片上传感器阵列

    公开(公告)号：US20080026503A1

    公开(公告)日：2008-01-31

    申请号：US11460459

    申请日：2006-07-27

    Applicant: Vivian Ryan

    Inventor： Vivian Ryan

    IPC: H01L21/00

    CPC classification number: G05D23/20 ,  G05D23/1928

    Abstract: Embodiments of the invention provide methods and apparatus for managing temperature in integrated circuits. In accordance with an aspect of the invention, an integrated circuit comprises a monitored region defined by three or more edges. What is more, the integrated circuit comprises at least two temperature sensors for each of the three or more edges. The temperatures sensors are arranged along the three or more edges such that each edge has substantially the same arrangement of temperature sensors. Thermal management of the integrated circuit may be accomplished by modifying functional aspects of the integrated circuit in response to measurements provided by the temperature sensors.

    Abstract translation: 本发明的实施例提供了用于管理集成电路中的温度的方法和装置。 根据本发明的一个方面，集成电路包括由三个或更多个边缘限定的监视区域。 此外，集成电路包括用于三个或更多个边缘中的每一个的至少两个温度传感器。 温度传感器沿着三个或更多个边缘布置，使得每个边缘具有基本相同的温度传感器布置。 集成电路的热管理可以通过响应于由温度传感器提供的测量来修改集成电路的功能方面来实现。

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