公开(公告)号：US11328976B1

公开(公告)日：2022-05-10

申请号：US16808023

申请日：2020-03-03

Applicant: XILINX, INC.

Inventor： Gamal Refai-Ahmed ,  Chi-Yi Chao ,  Suresh Ramalingam ,  Hoa Lap Do ,  Anthony Torza ,  Brian D. Philofsky

IPC: H01L23/367 ,  H01L23/467 ,  H01L23/473 ,  H01L23/42

Abstract: Some examples described herein provide for three-dimensional (3D) thermal management apparatuses for thermal energy dissipation of thermal energy generated by an electronic device. In an example, an apparatus includes a thermal management apparatus that includes a primary base, a passive two-phase flow thermal carrier, and fins. The thermal carrier has a carrier base and one or more sidewalls extending from the carrier base. The carrier base and the one or more sidewalls are a single integral piece. The primary base is attached to the thermal carrier. The carrier base has an exterior surface that at least a portion of which defines a die contact region. The thermal carrier has an internal volume aligned with the die contact region. A fluid is disposed in the internal volume. The fins are attached to and extend from the one or more sidewalls of the thermal carrier.

公开(公告)号：US20210193620A1

公开(公告)日：2021-06-24

申请号：US16718868

申请日：2019-12-18

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Cheang-Whang Chang

IPC: H01L25/065 ,  H01L23/04 ,  H01L23/31 ,  H01L23/367

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.

公开(公告)号：US10262920B1

公开(公告)日：2019-04-16

申请号：US15369607

申请日：2016-12-05

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Brian D. Philofsky ,  Anthony Torza

IPC: H01L23/22 ,  H01L23/24 ,  H01L23/427 ,  H01L23/055 ,  H01L23/367 ,  H01L23/10

Abstract: Chip packages and electronic devices are provided that include a thermal capacitance element that improves the operation of IC dies at elevated temperatures. In one example, a chip package is provided that includes an integrated circuit (IC) die, a lid thermally connected to the IC die, and a thermal capacitance element thermally connected to the lid. The thermal capacitance element includes a container and a capacitance material sealingly disposed in the container. The capacitance material has a phase transition temperature that is between 80 and 100 percent of a maximum designed operating temperature in degrees Celsius of the IC die.

公开(公告)号：US10096502B2

公开(公告)日：2018-10-09

申请号：US15360187

申请日：2016-11-23

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Mohsen H. Mardi ,  Tien-Yu Lee ,  Ivor G. Barber ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

IPC: B23P21/00 ,  H01L21/673 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56

Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.

公开(公告)号：US20180284187A1

公开(公告)日：2018-10-04

申请号：US15471390

申请日：2017-03-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Ivor G. Barber ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Tien-Yu Lee ,  Henley Liu ,  David M. Mahoney ,  Mohsen H. Mardi

IPC: G01R31/28

CPC classification number: G01R31/2891 ,  G01R31/2889

Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

公开(公告)号：US20180144963A1

公开(公告)日：2018-05-24

申请号：US15360187

申请日：2016-11-23

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Mohsen H. Mardi ,  Tien-Yu Lee ,  Ivor G. Barber ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

IPC: H01L21/673 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/67333 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/67109 ,  H01L23/3185 ,  H01L23/3675 ,  H01L24/16 ,  H01L2224/16227

Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.

公开(公告)号：US20170092619A1

公开(公告)日：2017-03-30

申请号：US14867349

申请日：2015-09-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Tien-Yu Lee ,  Ferdinand F. Fernandez ,  Suresh Ramalingam ,  Ivor G. Barber ,  Inderjit Singh ,  Nael Zohni

IPC: H01L25/065 ,  H01L23/06 ,  H01L23/373 ,  H01L25/00 ,  H01L23/00 ,  H01L23/10 ,  H01L23/367

CPC classification number: H01L23/373 ,  H01L21/4882 ,  H01L23/04 ,  H01L23/16 ,  H01L23/367 ,  H01L23/40 ,  H01L23/4006 ,  H01L23/473 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.

公开(公告)号：US11605886B1

公开(公告)日：2023-03-14

申请号：US17133518

申请日：2020-12-23

Applicant: XILINX, INC.

Inventor： Gamal Refai-Ahmed ,  Chi-Yi Chao ,  Lik Tsang ,  Jens Weis ,  Brendan Farley ,  Anthony Torza ,  Suresh Ramalingam

IPC: H01Q1/42 ,  H01L23/427 ,  H01Q1/02

Abstract: An antenna assembly is provided having passive cooling elements that enable compact design. In one example, an antenna assembly is provided that includes a heat sink assembly having an interior side and an exterior side, an antenna array, an antenna circuit board, and a radome. The antenna circuit board includes at least one integrated circuit (IC) die. The IC die has a conductive primary heat dissipation path to the interior side of the heat sink assembly. The radome is coupled to the heat sink assembly and encloses the antenna circuit board and the antenna array between the radome and the heat sink assembly. The heat sink assembly includes a metal base plate and at least a first heat pipe embedded with the metal base plate. The first heat pipe is disposed between the metal base plate and the IC die.

公开(公告)号：US11488936B2

公开(公告)日：2022-11-01

申请号：US16718868

申请日：2019-12-18

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Cheang-Whang Chang

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/04 ,  H01L23/31

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.

公开(公告)号：US11488887B1

公开(公告)日：2022-11-01

申请号：US16810473

申请日：2020-03-05

Applicant: XILINX, INC.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Boon Y. Ang ,  Toshiyuki Hisamura ,  Suresh Parameswaran ,  Scott McCann ,  Hoa Lap Do

IPC: H01L23/367 ,  H01L21/306 ,  H01L23/00 ,  H01L23/373

Abstract: In one example, a method includes providing a first side of a semiconductor substrate with a plurality of transistors, etching a second side of the substrate, opposite the first side, with a pattern of trenches, the trenches having a pre-defined depth and width, and providing the etched semiconductor substrate in a package. In one example, the predefined depth and width of the trenches is such so as to increase the surface area of the second side of the substrate by at least 20 percent. In one example, the method also includes providing a layer of a thermal interface material (TIM) on the second side of the substrate, including to fill at least a portion of the trenches.