公开(公告)号：US06643758B2

公开(公告)日：2003-11-04

申请号：US09984357

申请日：2001-10-30

申请人： Takaaki Furuyama ,  Mitsuhiro Nagao

发明人： Takaaki Furuyama ,  Mitsuhiro Nagao

IPC分类号： G06F1200

CPC分类号： G11C16/08 ,  G06F12/0653 ,  G06F2212/2022 ,  G11C16/20

摘要： According to one aspect of the present invention, the flash memory comprises a memory region divided into a plurality of real banks, wherein from among the plurality of products which consists of a plurality of combinations of virtual banks having at least one real bank; and a combination of the top boot in which the most significant address is allocated to the boot bank having the boot sector and the bottom boot in which the least significant address is allocated to the boot bank, product information data are set in a product information record section, whereby any product can be configured.

公开(公告)号：US5787046A

公开(公告)日：1998-07-28

申请号：US636801

申请日：1996-04-23

申请人： Takaaki Furuyama ,  Akira Sugiura

发明人： Takaaki Furuyama ,  Akira Sugiura

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C13/00

CPC分类号： G11C7/10 ,  G11C7/1015

摘要： A semiconductor memory device is operable in an operation mode selected from a read mode, a normal write mode and a block write mode. The memory device includes a memory cell array having a plurality of pairs of bit lines, a plurality of word lines and a plurality of memory cells provided at intersections of the bit lines and the word lines, wherein each pair of the bit lines and the memory cells associated with each bit line pair form one of a plurality of columns defined in the memory cell array. The memory device also includes a pair of data lines and a column selection controller, wherein the column selection controller is supplied with a group of column selection signals for selectively connecting and disconnecting the pair of data lines to and from the plurality of pairs of bit lines. In response to the group of column selection signals with a first signal output pattern for use in the normal write mode or the read mode, the column selection controller selects one of the plurality of columns to connect the pair of data lines to a pair of bit lines associated with the select column. Further, in response to the group of column selection signals with a second signal output pattern for use in the block write mode, the column selection controller selects at least two of the plurality of columns to connect the pair of data lines to the bit line pairs associated with a column block as a group of the selected columns.

摘要翻译： 半导体存储器件可以在从读取模式，正常写入模式和块写入模式中选择的操作模式中操作。 存储器件包括存储单元阵列，其具有多个位线对，多个字线和设置在位线和字线的交点处的多个存储单元，其中每对位线和存储器 与每个位线对相关联的单元形成在存储单元阵列中定义的多个列之一。 存储装置还包括一对数据线和列选择控制器，其中列选择控制器被提供有一组列选择信号，用于选择性地连接和断开与多对位线对之间的数据线对 。 响应于具有用于正常写入模式或读取模式的第一信号输出模式的列选择信号组，列选择控制器选择多个列之一将数据线对连接到一对位 与选择列关联的行。 此外，响应于具有用于块写入模式的第二信号输出模式的列选择信号组，列选择控制器选择多个列中的至少两个将数据线对连接到位线对 与列块相关联，作为所选列的组。

公开(公告)号：US5594699A

公开(公告)日：1997-01-14

申请号：US308105

申请日：1994-09-16

申请人： Yukihiro Nomura ,  Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

发明人： Yukihiro Nomura ,  Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

IPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/143

摘要： A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

摘要翻译： 具有多个存储单元的DRAM（动态随机存取存储器）包括数据读/写电路读取或写入存储单元的数据，自刷新电路刷新存储在存储单元中的数据，以及电源单元， 数据读/写电路和自刷新电路的电力，电力在正常操作模式下具有第一电压电平，在自刷新模式下具有第二电压电平，其中第二电压电平低于 第一电压电平。

公开(公告)号：US4932000A

公开(公告)日：1990-06-05

申请号：US355630

申请日：1989-05-23

申请人： Yukinori Kodama ,  Takaaki Furuyama

发明人： Yukinori Kodama ,  Takaaki Furuyama

IPC分类号： G11C11/407 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

摘要： A semiconductor memory device includes: a memory cell array including a plurality of word lines; a row pre-decoding unit responsive to a row address signal, outputting a plurality of row pre-decode signals with units of a group having signals of a number corresponding to a combination of each logic level of a predetermined plurality of bits of the row address signal; a row pre-decode wiring for transmitting the plurality of row pre-decode signals; a row main decoder responsive to one signal in each group of the plurality of row pre-decode signals, carrying out a main decoding for selecting one of the plurality of word lines; a pseudo row decoder having substantially same electrical characteristics as the row main decoder, carrying out a simulation of the main decoding in response to the plurality of row pre-decode signals output on row pre-decode wiring; and a word line driver for driving a word line selected by the row main decoder to a predetermined level. An operation of the word line driver is started in response to an activation of the pseudo row decoder, thereby excluding a possibility of an erroneous selection of a word line and preventing an unnecessary prolongation of an access time.

公开(公告)号：US08094478B2

公开(公告)日：2012-01-10

申请号：US12878656

申请日：2010-09-09

申请人： Takaaki Furuyama ,  Makoto Niimi ,  Masahiro Niimi

发明人： Takaaki Furuyama ,  Makoto Niimi ,  Masahiro Niimi

IPC分类号： G11C5/06

CPC分类号： G11C16/12

摘要： A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC1 and a first ground line VSS1 are connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unit 5 to which a second power source line VCC2 and a second ground line VSS2 are connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unit 2 and the read control unit 5 are arranged so as to be spaced from each another.

摘要翻译： 提供一种能够防止读取操作和重写操作之间的干扰并且能够防止在存储器块之间同时执行读取操作和重写操作的情况下可能发生的故障的非易失性存储器件1。 非易失性存储器件1设有多个存储体，重写控制单元2，第一电源线VCC1和第一接地线VSS1连接到该重写控制单元2，并且其适于控制相对于存储体i的重写操作， 以及连接有第二电源线VCC2和第二接地线VSS2并且适于控制相对于存储体j的读取操作的读取控制单元5，其中重写控制单元2和读取控制单元5 被布置成彼此间隔开。

公开(公告)号：US20090323435A1

公开(公告)日：2009-12-31

申请号：US12341886

申请日：2008-12-22

申请人： Makoto Niimi ,  Kenji Nagai ,  Takaaki Furuyama

发明人： Makoto Niimi ,  Kenji Nagai ,  Takaaki Furuyama

IPC分类号： G11C7/10

CPC分类号： G11C7/1078 ,  G06F1/10 ,  G11C7/109

摘要： In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.

摘要翻译： 在本发明的存储装置中，响应于锁存控制信号对一系列信号进行锁存控制。 设置锁存控制信号的锁存控制端子和分别输入一系列信号的多个信号端子。 这里，分别提供多个锁存电路以对应于多个信号端子。 多个锁存电路分别位于与其相关联的信号端子规定距离内并且距离锁存器控制端子在指定距离内。 从信号端子到其相关联的锁存电路的信号传输的延迟可以被均衡，并且来自锁存控制端子的信号传输的延迟被输入到锁存电路，锁存控制端子用于执行锁存控制的信号被输入到锁存电路。 这有助于减少信号的锁存特性的偏移。

公开(公告)号：US20060209583A1

公开(公告)日：2006-09-21

申请号：US11341029

申请日：2006-01-27

申请人： Shozo Kawabata ,  Kenji Shibata ,  Takaaki Furuyama ,  Satoru Kawamoto

发明人： Shozo Kawabata ,  Kenji Shibata ,  Takaaki Furuyama ,  Satoru Kawamoto

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.

摘要翻译： 半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。 利用这种结构，将不同的行地址分配给操作设置信息的各个功能。 因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。

公开(公告)号：US06977411B2

公开(公告)日：2005-12-20

申请号：US10738025

申请日：2003-12-18

申请人： Masaki Ito ,  Masaya Katayama ,  Takaaki Furuyama ,  Shozo Kawabata

发明人： Masaki Ito ,  Masaya Katayama ,  Takaaki Furuyama ,  Shozo Kawabata

IPC分类号： H01L27/10 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883

摘要： The semiconductor device comprises a first well 14 of a first conduction type formed in a semiconductor substrate 10; a second well 16 of a second conduction type formed in the first well 14; and a transistor 40 including a control gate 18 formed of an impurity region of the first conduction type formed in the second well 16, a first impurity diffused layer 26 and a second impurity diffused layer 33 formed with a channel region 25 therebetween, and a floating gate electrode 20 formed on the channel region 25 and the control gate 18 with a gate insulation film 24 therebetween. The control gate 18 is buried in the semiconductor substrate 10, which makes it unnecessary to form the control gate 18 on the floating gate electrode 20. Thus, the memory transistor and the other transistors, etc. can be formed by the same fabricating process. Thus, the fabrication processes can be less and the semiconductor device can be inexpensive.

摘要翻译： 半导体器件包括形成在半导体衬底10中的第一导电类型的第一阱14; 形成在第一阱14中的第二导电类型的第二阱16; 以及晶体管40，其包括由形成在第二阱16中的第一导电类型的杂质区域形成的控制栅极18，在其间形成有沟道区域25的第一杂质扩散层26和第二杂质扩散层33，以及浮置 栅极电极20形成在沟道区域25和控制栅极18之间，栅极绝缘膜24在其间。 控制栅极18被埋在半导体衬底10中，这使得不必在浮栅电极20上形成控制栅极18。 因此，可以通过相同的制造工艺来形成存储晶体管和其它晶体管等。 因此，制造工艺可以更少，并且半导体器件可以是便宜的。

公开(公告)号：US06917541B2

公开(公告)日：2005-07-12

申请号：US10060185

申请日：2002-02-01

申请人： Koji Shimbayashi ,  Takaaki Furuyama

发明人： Koji Shimbayashi ,  Takaaki Furuyama

IPC分类号： G11C16/06 ,  G11C7/18 ,  G11C16/04 ,  G11C16/24 ,  G11C16/28

CPC分类号： G11C16/24 ,  G11C7/18 ,  G11C16/28

摘要： This invention provides a nonvolatile semiconductor memory device including a novel memory core portion in which an influence of a parasitic element component in a memory cell information reading path is excluded in a reading operation, and novel sensing means accompanying this memory core structure, so as to achieve rapid sensing. In the memory core portion, a selected memory cell is selected by a global bit line through a local bit line and an adjacent global bit line is connected to a local bit line in a non-selected sector. A column selecting portion connects a pair of the global bit lines to a pair of data bus lines. A load portion having a load equivalent to a parasitic capacitance of a path leading from the memory cell and for supplying a reference current to a reference side is connected to a pair of the data bus lines. A current of the memory cell information is compared with the reference current by a current comparing portion and a differential current is outputted. A path load is equalized by a pair of adjacent paths so that an effect from noise is canceled, thus making it possible to achieve rapid reading.

摘要翻译： 本发明提供了一种非易失性半导体存储器件，其包括新颖的存储器芯部分，其中在读取操作中排除了存储器单元信息读取路径中的寄生元件分量的影响，以及伴随该存储器核心结构的新型感测装置， 实现快速感知。 在存储器核心部分中，通过局部位线的全局位线选择选定的存储单元，并且相邻的全局位线连接到非选择扇区中的本地位线。 列选择部分将一对全局位线连接到一对数据总线。 具有与从存储单元引出的路径的寄生电容相当并且用于向参考侧提供参考电流的负载的负载部分连接到一对数据总线。 通过电流比较部分将存储单元信息的电流与参考电流进行比较，并输出差分电流。 路径负载由一对相邻的路径相等，从而消除噪声的影响，从而可以实现快速读取。

公开(公告)号：US20050141277A1

公开(公告)日：2005-06-30

申请号：US11062662

申请日：2005-02-23

申请人： Takaaki Furuyama

发明人： Takaaki Furuyama

IPC分类号： G11C16/02 ,  G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0433 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/30 ,  G11C2216/10 ,  G11C2216/14 ,  G11C2216/16

摘要： A non-volatile memory in which a plurality of memory cells connected to a same word line are entirely written with data. Source lines SL separated from each other in column units is arranged on each memory cell of a memory cell array. When writing data, one of either a first or a second source voltage is applied to each source line in accordance with data that is to be written. After a first control voltage of negative voltage is applied, a second control voltage of high voltage is applied to the word line with the voltage of each source line SL in a maintained state. Therefore, each memory cell is erased or programmed in accordance with the voltage applied to the respective source line.

摘要翻译： 连接到同一字线的多个存储单元完全用数据写入的非易失性存储器。 在列单元中彼此分离的源极线SL布置在存储器单元阵列的每个存储单元上。 当写入数据时，根据要写入的数据将第一或第二源电压中的一个施加到每个源极线。 在施加负电压的第一控制电压之后，将高电压的第二控制电压施加到字线，并且每个源极线SL的电压处于维持状态。 因此，每个存储单元根据施加到相应源极线的电压被擦除或编程。