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    Multi stage resistive ladder network having extra stages for trimming
    11.
    发明授权
    Multi stage resistive ladder network having extra stages for trimming 失效
    多级电阻梯形网络具有额外的修整阶段

    公开(公告)号：US4338590A

    公开(公告)日：1982-07-06

    申请号：US110135

    申请日：1980-01-07

    Applicant: Joseph J. Connolly, Jr. ,  James B. Cecil

    Inventor： Joseph J. Connolly, Jr. ,  James B. Cecil

    IPC: H03M1/00 ,  H03K13/02

    CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/3115 ,  H03M2201/3131 ,  H03M2201/3136 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/6121 ,  H03M2201/63 ,  H03M2201/814

    Abstract: A multi-stage resistive ladder network which uses extra stages to trim out resistance discrepencies. All of the stages are interconnected in a series. Nominally, current is divided in half within each stage. Half of the current is gated onto a bus in response to logic control signals, and the other half of the current is passed onto the next succeeding stage. Due to various processing limitations, the resistors comprising each stage vary slightly from their nominal value, which in turn upsets the current division. To compensate for this additional current dividing stages are serially connected to the last stage of the ladder. Current from these additional stages are selectively coupled onto the bus in response to the logic signals in addition to the current which is normally coupled thereto.

    Abstract translation: 一个多级电阻梯形网络，使用额外的级来修剪阻抗差异。 所有的阶段都是相互联系的。 名义上，目前在每个阶段都分成两半。 响应于逻辑控制信号，一半的电流被门控在总线上，而另一半的电流被传递到下一个后续阶段。 由于各种处理限制，包括每个级的电阻器与它们的标称值略有不同，这反过来扰乱了当前的划分。 为了补偿这个额外的电流分级级与梯子的最后阶段串联连接。 来自这些附加级的电流除了通常耦合到其上的电流之外还响应于逻辑信号而选择性地耦合到总线上。

    All-digital delay-locked loop circuit based on time-to-digital converter and control method thereof
    15.
    发明授权
    All-digital delay-locked loop circuit based on time-to-digital converter and control method thereof 有权
    基于时间 - 数字转换器的全数字延迟锁定环路及其控制方法

    公开(公告)号：US09568890B1

    公开(公告)日：2017-02-14

    申请号：US15226323

    申请日：2016-08-02

    Applicant: Hongik University Industry-Academia Cooperation

    Inventor： Jong Sun Kim

    IPC: H03M1/50 ,  G04F10/00 ,  H03L7/089 ,  H03K5/156 ,  H03L7/18 ,  H03L7/081 ,  H03M1/56

    CPC classification number: H03L7/0814 ,  H03K5/1565 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/18 ,  H03M1/56 ,  H03M2201/4233

    Abstract: Disclosed is an all-digital delay locked loop circuit based on a time-to-digital converter and a control method thereof. The all-digital delay locked loop circuit includes a phase inversion locking control circuit for determining whether or not to use a phase inversion locking algorithm by detecting a phase difference between an input clock and an output clock and outputting the input clock or an inverted input clock; and a phase synchronization unit connected to an output terminal of the phase inversion locking control circuit to receive an output signal of the phase inversion locking control circuit and a control signal and perform phase synchronization, in which the phase synchronization unit includes a digital control delay line for receiving the input clock or the inverted input clock output from the phase inversion locking control circuit and reducing a phase error between the input clock and the output clock.

    Abstract translation: 公开了一种基于时间 - 数字转换器的全数字延迟锁定环路电路及其控制方法。 全数字延迟锁定环电路包括相位锁定控制电路，用于通过检测输入时钟和输出时钟之间的相位差并输出输入时钟或反相输入时钟来确定是否使用相位反转锁定算法 ; 以及相位同步单元，连接到相位锁定控制电路的输出端子，以接收相位锁定控制电路的输出信号和控制信号，并执行相位同步，其中相位同步单元包括数字控制延迟线 用于接收从相位锁定控制电路输出的输入时钟或反相输入时钟，并减少输入时钟与输出时钟之间的相位误差。

    Background Calibration of Time-Interleaved Analog-to-Digital Converters
    16.
    发明申请
    Background Calibration of Time-Interleaved Analog-to-Digital Converters 有权
    时间交错模数转换器的背景校准

    公开(公告)号：US20160149582A1

    公开(公告)日：2016-05-26

    申请号：US14554790

    申请日：2014-11-26

    Applicant: Silicon Laboratories Inc.

    Inventor： Kareem A. Ragab ,  John Khoury

    IPC: H03M1/10 ,  H03M1/12 ,  H03M1/06

    CPC classification number: H03M1/1023 ,  H03M1/00 ,  H03M1/0626 ,  H03M1/0695 ,  H03M1/1004 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/124 ,  H03M2201/4233

    Abstract: A robust and fast background calibration technique for correction of time-interleaved ADC offset, gain, bandwidth, and timing mismatches is proposed. The technique combines the use of a calibration signal and a reference ADC. The calibration signal enhances robustness and makes the technique independent of the input signal's statistics. The reference ADC speeds up convergence and enables the use of a small amplitude calibration signal that does not significantly reduce the input signal dynamic range. The calibration signal can be subtracted or filtered from the ADC output and is therefore invisible to the ADC user.

    Abstract translation: 提出了用于校正时间交织的ADC偏移，增益，带宽和时序不匹配的鲁棒且快速的背景校准技术。 该技术结合使用校准信号和参考ADC。 校准信号增强了鲁棒性，使得该技术独立于输入信号的统计。 参考ADC可以加快收敛速度​​，并且可以使用不会显着降低输入信号动态范围的小幅度校准信号。 校准信号可以从ADC输出中减去或滤波，因此ADC用户不可见。

    Comparison circuits
    17.
    发明授权
    Comparison circuits 有权
    比较电路

    公开(公告)号：US08988265B2

    公开(公告)日：2015-03-24

    申请号：US13941598

    申请日：2013-07-15

    Applicant: MediaTek Inc.

    Inventor： Yun-Shiang Shu

    IPC: H03M1/12 ,  H03M1/50 ,  H03M1/20 ,  H03M1/00 ,  H03M1/36

    CPC classification number: H03M1/50 ,  H03M1/00 ,  H03M1/12 ,  H03M1/206 ,  H03M1/365 ,  H03M2201/4233

    Abstract: A comparison circuit is provided and includes first and second comparators and a first time-to-digital comparator. The first comparator with a first offset voltage receives an input signal and generates a first comparison signal and a first inverse comparison signal. The second comparator receives the input signal and generates a second comparison signal and a second inverse comparison signal. The first offset voltage is larger than the second offset voltage. The first time-to-digital comparator receives the first comparison signal and the second inverse comparison signal and generates first and second determination signals according to the first comparison signal and the second inverse comparison signal. The first and second determination signals indicate whether a voltage of the input signal is larger than a first middle voltage. The first middle voltage is equal to a half of the sum of the first offset voltage and the second offset voltage.

    Abstract translation: 提供比较电路并包括第一和第二比较器和第一时间 - 数字比较器。 具有第一偏移电压的第一比较器接收输入信号并产生第一比较信号和第一反比较信号。 第二比较器接收输入信号并产生第二比较信号和第二反比较信号。 第一偏移电压大于第二偏移电压。 第一时间数字比较器接收第一比较信号和第二反比较信号，并根据第一比较信号和第二反比较信号产生第一和第二确定信号。 第一和第二确定信号指示输入信号的电压是否大于第一中间电压。 第一中间电压等于第一偏移电压和第二偏移电压之和的一半。

    TIME-TO-DIGITAL CONVERTER
    18.
    发明申请
    TIME-TO-DIGITAL CONVERTER 有权
    时间到数字转换器

    公开(公告)号：US20150077279A1

    公开(公告)日：2015-03-19

    申请号：US14029699

    申请日：2013-09-17

    Applicant: QUALCOMM Incorporated

    Inventor： Hui William Song ,  Mohamed Hassan Abu-Rahma

    IPC: H03M1/12

    CPC classification number: G04F10/005 ,  H03H11/265 ,  H03K5/135 ,  H03L7/0814 ,  H03M1/00 ,  H03M1/12 ,  H03M2201/4233 ,  H04M1/505

    Abstract: Time-to-digital converters (TDC) with improved resistance to metastability are provided. The TDC includes a ring oscillator gated by a start signal. A stop signal triggers capturing values of phase signals from the ring oscillator using master-slave flip-flops. Signals from two of the master stages of the flip-flops are logically combined to produce a counter clock signal that causes a counter to count. The outputs of the flip-flops and of the counter are encoded to produce a digital representation of the time between transitions of the start signal and the stop signal. Since the signals from the master stages of flip-flops are captured (and stop toggling) by the stop signal, the counter clock signal stops toggling, and the counter stops counting. This assures that the values of the captured phase signals and the counter are consistent and avoids metastability errors that could otherwise occur.

    Abstract translation: 提供了具有改进的抗亚稳性的时间 - 数字转换器（TDC）。 TDC包括由起始信号选通的环形振荡器。 停止信号触发使用主从触发器捕获来自环形振荡器的相位信号的值。 来自触发器的两个主级的信号被逻辑地组合以产生使计数器计数的计数器时钟信号。 触发器和计数器的输出被编码以产生开始信号和停止信号的转变之间的时间的数字表示。 由于来自触发器的主级的信号被停止信号捕获（并停止切换），所以计数器时钟信号停止翻转，并且计数器停止计数。 这确保捕获的相位信号和计数器的值是一致的，并且避免可能发生的亚稳态误差。

    ANALOGUE-TO-DIGITAL CONVERTER
    20.
    发明申请
    ANALOGUE-TO-DIGITAL CONVERTER 有权
    模拟数字转换器

    公开(公告)号：US20130321190A1

    公开(公告)日：2013-12-05

    申请号：US13902638

    申请日：2013-05-24

    Applicant: Wolfson Microelectronics pic

    Inventor： John Paul Lesso ,  John Laurence Pennock

    IPC: H03M1/34

    CPC classification number: H03M1/00 ,  H03M1/1014 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/186 ,  H03M1/34 ,  H03M1/60 ,  H03M2201/4233

    Abstract: An apparatus and method for regulating analogue-to-digital converters. First and second input signals are received at controlled oscillator circuitry which generates respective first and second pulse streams with pulse rates based on the relevant input signal. Difference circuitry determines the difference in number of pulses of the first and second pulse streams and outputs a first digital signal. Circuitry also determines a signal independent value based on the number of pulses of the first and/or second pulse streams. In one embodiment this value is the sum or average of the number of pulses of the first and second pulse streams. This value can be used to calibrate for any variation in transfer characteristic of the oscillator circuitry. In one embodiment this value is compared to a reference value and a regulation signal passed to control circuitry to regulate the operation of the oscillation circuitry.

    Abstract translation: 一种用于调节模数转换器的装置和方法。 在受控振荡器电路处接收第一和第二输入信号，该电路产生具有基于相关输入信号的脉冲速率的相应的第一和第二脉冲流。 差分电路确定第一和第二脉冲流的脉冲数的差异并输出第一数字信号。 电路还基于第一和/或第二脉冲流的脉冲数来确定与信号无关的值。 在一个实施例中，该值是第一和第二脉冲流的脉冲数的和或平均值。 该值可用于校准振荡器电路的传输特性的任何变化。 在一个实施例中，该值与参考值和传递给控制电路的调节信号进行比较以调节振荡电路的操作。

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