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公开(公告)号：US11711918B2
公开(公告)日：2023-07-25
申请号：US17227793
申请日：2021-04-12
发明人： Kyung Hwan Lee , Yong Seok Kim , Hyun Cheol Kim , Satoru Yamada , Sung Won Yoo , Jae Ho Hong
摘要： Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.
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公开(公告)号：US11700730B2
公开(公告)日：2023-07-11
申请号：US17129146
申请日：2020-12-21
发明人： Sanh D. Tang , John K. Zahurak
IPC分类号： H01L27/11582 , H01L27/11551 , H10B43/27 , H01L21/28 , H01L27/06 , H01L29/66 , H01L29/788 , H01L29/792 , H10B41/10 , H10B41/20 , H10B41/27 , H10B41/50 , H10B43/10 , H10B43/20 , H10B43/50 , H10B63/00 , H01L21/768 , G11C13/00 , G11C16/10 , G11C16/14 , G11C16/26 , H01L23/528 , H10N70/20
CPC分类号： H10B43/27 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C16/10 , G11C16/14 , G11C16/26 , H01L21/76838 , H01L23/528 , H01L27/0688 , H01L29/40114 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H10B41/10 , H10B41/20 , H10B41/27 , H10B41/50 , H10B43/10 , H10B43/20 , H10B43/50 , H10B63/34 , H10B63/845 , G11C2213/71 , H10N70/231
摘要： Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.
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公开(公告)号：US11700727B2
公开(公告)日：2023-07-11
申请号：US17111275
申请日：2020-12-03
IPC分类号： H10B41/27 , G11C5/06 , G11C5/02 , H10B43/27 , H10B43/10 , H10B43/50 , H10B41/35 , H10B41/50 , H10B43/35
CPC分类号： H10B41/27 , G11C5/025 , G11C5/06 , H10B41/35 , H10B41/50 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/50
摘要： A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The stack structure comprises a first block structure comprising stair step structures spaced from each other by crest regions, the stair step structures each comprising steps defined at horizontal edges of the tiers of the conductive structures and the insulative structures, and a second block structure horizontally neighboring the first block structure and comprising additional stair step structures spaced from one another by additional crest regions, the additional stair step structures horizontally offset from the stair step structures of the first block structure, and a slot structure extending though the stack structure and interposed between the first block structure and the second block structure. Related microelectronic devices, electronic systems, and methods are also described.
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14.发明公开公开(公告)号：US20240292628A1
公开(公告)日：2024-08-29
申请号：US18442792
申请日：2024-02-15
发明人： Akihiro TOBIOKA
CPC分类号： H10B43/50 , H01L23/5226 , H01L23/562 , H10B41/27 , H10B41/50 , H10B43/27
摘要： A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers. The alternating stacks are laterally spaced apart among one another by backside isolation assemblies. At least one of the backside isolation assemblies generally extends along a first horizontal direction with lateral undulations along a second horizontal direction that is perpendicular to the first horizontal direction. At least one of the alternating stacks has a modulation in width along the second horizontal direction as a function of a position along the first horizontal direction. Memory stack structures vertically extend through a respective one of the alternating stacks. Each of the backside isolation assemblies includes a respective laterally alternating sequence of backside dielectric isolation walls and backside dielectric support pillar structures.
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公开(公告)号：US20240276731A1
公开(公告)日：2024-08-15
申请号：US18641654
申请日：2024-04-22
申请人： SK hynix Inc.
发明人： Eun Seok CHOI
IPC分类号： H10B43/50 , H01L23/535 , H10B41/27 , H10B41/41 , H10B41/50 , H10B43/27 , H10B43/40 , H10B63/00
CPC分类号： H10B43/50 , H01L23/535 , H10B41/27 , H10B41/41 , H10B41/50 , H10B43/27 , H10B43/40 , H10B63/34 , H10B63/845
摘要： A semiconductor device includes a stacked body including stacked insulating layers and stacked conductive layers; a cell plug; a connection contact structure; and a source layer coupled to the cell plug. The cell plug includes upper and lower portions, the connection contact structure includes a first connection contact disposed at substantially the same level as the lower portion of the cell plug, and a second connection contact disposed at substantially the same level as the upper portion thereof, a level at which the first and second connection contacts contact each other is substantially the same as a level at which the upper and lower portions of the cell plug contact each other, and a level of an uppermost portion of the second connection contact is higher than a level of a bottom surface of the source layer, and is lower than a level of a top surface thereof.
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公开(公告)号：US20240224524A1
公开(公告)日：2024-07-04
申请号：US18604811
申请日：2024-03-14
摘要： Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. Doped-semiconductor-material is within the intermediate region and is configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US20240178168A1
公开(公告)日：2024-05-30
申请号：US18237962
申请日：2023-08-25
发明人： Jaeho KIM , Woosung YANG , Joonyoung KWON , Jiyoung KIM , Sukkang SUNG
CPC分类号： H01L24/08 , H10B41/50 , H10B43/50 , H01L2224/08145
摘要： A semiconductor device includes a first substrate structure including a substrate, circuit elements on the substrate, a first interconnection structure on the circuit elements, and first metal bonding layers on the first interconnection structure; and a second substrate structure connected to the first substrate structure, and the second substrate structure includes: a plating layer; gate electrodes stacked and spaced apart from each other in a first direction below the plating layer; channel structures penetrating through the gate electrodes and extending in the first direction; a separation region penetrating through the gate electrodes and extending in a second direction; a second interconnection structure below the gate electrodes and the channel structures; second metal bonding layers below the second interconnection structure and connected to the first metal bonding layers; and dummy pattern layers between the second metal bonding layers, extending in the second direction, and including an insulating material.
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公开(公告)号：US20240155844A1
公开(公告)日：2024-05-09
申请号：US18415460
申请日：2024-01-17
发明人： Myung Hun Lee , Dong Ha Shin , Pan Suk Kwak , Dae Seok Byeon
摘要： A semiconductor memory device includes a mold structure including gate electrodes stacked on a first substrate, a channel structure that penetrates a first region of the mold structure to cross the gate electrodes, a first through structure that penetrates a second region of the mold structure, and a second through structure that penetrates a third region of the mold structure. The mold structure further includes memory cell blocks extending in a first direction and spaced apart in a second direction, and a dummy block extending in the first direction and disposed between the memory cell blocks. Each of the memory cell blocks and the dummy block includes a cell region and an extension region arranged in the first direction. The first region is the cell region of one of the memory cell blocks, the second region is the extension region of the one of the memory cell blocks, and the third region is the extension region of the dummy block.
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公开(公告)号：US20240130134A1
公开(公告)日：2024-04-18
申请号：US18396042
申请日：2023-12-26
申请人： SK hynix Inc.
发明人： Jae Taek KIM , Hye Yeong JUNG
IPC分类号： H10B43/50 , H01L23/522 , H01L23/528 , H10B41/10 , H10B41/40 , H10B41/50 , H10B43/10 , H10B63/00
CPC分类号： H10B43/50 , H01L23/5226 , H01L23/528 , H10B41/10 , H10B41/40 , H10B41/50 , H10B43/10 , H10B63/30 , H10B41/27
摘要： A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side surface and a step top surface. The peripheral contact structure is in contact with the step side surface.
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20.发明公开公开(公告)号：US20240099014A1
公开(公告)日：2024-03-21
申请号：US18524552
申请日：2023-11-30
发明人： Shunsuke TAKUMA , Yuji TOTOKI , Seiji SHIMABUKURO , Tatsuya HINOUE , Kengo KAJIWARA , Akihiro TOBIOKA
CPC分类号： H10B43/50 , H01L23/5226 , H01L23/562 , H10B41/27 , H10B41/50 , H10B43/27
摘要： At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.
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