公开(公告)号：US20160352364A1

公开(公告)日：2016-12-01

申请号：US15234122

申请日：2016-08-11

Applicant: STMICROELECTRONICS, INC.

Inventor： SIVAGNANAM PARTHASARATHY ,  LUN BIN HUANG ,  ALESSANDRO RISSO

IPC: H03M13/41 ,  H04L1/00 ,  H03M13/39

CPC classification number: H03M13/4146 ,  G06F11/1076 ,  G11B20/18 ,  H03M13/3905 ,  H03M13/3927 ,  H03M13/4184 ,  H03M13/42 ,  H03M13/6343 ,  H03M13/6502 ,  H04L1/0054 ,  H04L1/0055

Abstract: A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.

Abstract translation: 修改的软输出维特比算法（SOVA）检测器接收软信息值序列，并为每个软信息值确定最佳路径和备用路径，并且进一步确定当给定软件的最佳和替代路径导致相同值时 信息值，是否存在离开替代路径的第三路径，其导致相对于给定软信息值的最佳路径的相反决定。 然后，SOVA检测器在更新最佳路径的可靠性时考虑第三条路径。 改进的SOVA检测器通过Fossorier方法有效地实现了最大对数映射的等效性，并且包括SOVA检测器的前N个级的修正的可靠性度量单位，其中N是给定路径的存储器深度，并且包括用于 检测器的剩余阶段。

公开(公告)号：US09508560B1

公开(公告)日：2016-11-29

申请号：US14743511

申请日：2015-06-18

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Yann Mignot ,  Brown C. Peethala ,  Shariq Siddiqui

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/027

CPC classification number: H01L21/31116 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/76816

Abstract: A method that allows effective removal of a silicon-containing antireflective coating (SiARC) layer in a block mask after defining an unblock area in a sidewall image transfer (SIT) patterning process without causing a height loss of the SIT spacers is provided. The method includes first modifying the SiARC layer with a dry etch utilizing an etching gas comprising a nitrogen gas followed by treating the modified SiARC layer with a wet chemical etch utilizing an aqueous solution including dilute hydrofluoric acid and citric acid.

Abstract translation: 提供一种在限制了侧壁图像转印（SIT）图案化工艺中的未封闭区域而不引起SIT间隔物的高度损失之前有效去除块掩模中的含硅抗反射涂层（SiARC）层的方法。 该方法包括首先利用包含氮气的蚀刻气体进行干法蚀刻来修饰SiARC层，然后利用包含稀氢氟酸和柠檬酸的水溶液进行湿化学蚀刻来处理改性的SiARC层。

公开(公告)号：US09502292B2

公开(公告)日：2016-11-22

申请号：US14856949

申请日：2015-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/20 ,  H01L21/425 ,  H01L21/768 ,  H01L21/762 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

公开(公告)号：US09496415B1

公开(公告)日：2016-11-15

申请号：US14956815

申请日：2015-12-02

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L21/8234 ,  H01L27/146 ,  H01L29/786 ,  H01L29/66 ,  H01L29/24 ,  H01L29/49

CPC classification number: H01L29/78693 ,  H01L21/823437 ,  H01L27/14614 ,  H01L29/247 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

Abstract: Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material.

Abstract translation: 工艺和翻转的薄膜器件结构通常包括具有由三个面限定的凹形形状的金属栅极。 这些工艺通常包括形成翻转的薄膜器件结构，使得沟道与金属栅极自对准，并且触点可以与牺牲材料自对准。

公开(公告)号：US09490168B1

公开(公告)日：2016-11-08

申请号：US14710894

申请日：2015-05-13

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/535 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract translation: 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。

公开(公告)号：US09484535B1

公开(公告)日：2016-11-01

申请号：US14960712

申请日：2015-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L21/4763 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line.

Abstract translation: 在支撑衬底上形成电阻随机存取存储器（RRAM）结构，并且包括第一电极和第二电极。 第一电极由支撑衬底上的硅化物翅片和覆盖硅化物翅片的第一金属衬垫层制成。 具有可配置电阻性能的电介质材料层覆盖第一金属衬垫的至少一部分。 第二电极由覆盖电介质材料层的第二金属衬垫层和与第二金属衬垫层接触的金属填充物制成。 非易失性存储单元包括电连接在存取晶体管和位线之间的RRAM结构。

公开(公告)号：US20160300857A1

公开(公告)日：2016-10-13

申请号：US14680392

申请日：2015-04-07

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang ,  Walter Kleemeier

IPC: H01L27/12 ,  H01L29/417 ,  H01L27/092 ,  H01L21/324 ,  H01L21/306 ,  H01L29/08 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/41783 ,  H01L29/66545

Abstract: A junctionless field effect transistor on an insulating layer of a substrate includes a fin made of semiconductor material doped with a dopant of a first conductivity type. A channel made of an epitaxial semiconductor material region doped with a dopant of a second conductivity type is in contact with a top surface of the fin. An insulated metal gate straddles the channel. A source connection is made to the epitaxial semiconductor material region on one side of said insulated metal gate, and a drain connection is made to the epitaxial semiconductor material region on an opposite side of said insulated metal gate. The epitaxial channel may further be grown from and be in contact with opposed side surfaces of the fin.

Abstract translation: 在基板的绝缘层上的无连接场效应晶体管包括由掺杂有第一导电类型的掺杂剂的半导体材料制成的鳍。 由掺杂有第二导电类型的掺杂剂的外延半导体材料区域形成的沟道与鳍片的顶表面接触。 绝缘金属门横跨通道。 源极连接到所述绝缘金属栅极的一侧上的外延半导体材料区域，并且在所述绝缘金属栅极的相对侧上的外延半导体材料区域进行漏极连接。 外延沟道还可以从翅片的相对的侧表面生长并与其接触。

公开(公告)号：US09466452B1

公开(公告)日：2016-10-11

申请号：US14675359

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01H11/00 ,  H01H59/00

CPC classification number: H01L29/84 ,  B82B3/00 ,  H01H1/0094 ,  H01H49/00 ,  H01H50/005 ,  H01H59/0009 ,  H01H2001/0084 ,  H01L21/02532 ,  H01L21/30608

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

Abstract translation: 纳米级机电开关形式的集成晶体管消除了CMOS电流泄漏并提高了开关速度。 纳米尺度的机电开关具有从衬底的一部分延伸到空腔中的半导体悬臂。 悬臂响应于施加到晶体管栅极的电压而弯曲，从而在栅极下形成导电沟道。 当设备关闭时，悬臂返回到静止位置。 悬臂的这种运动打破了电路，恢复了阻挡电流的门下方的空隙，从而解决了泄漏问题。 纳米机电开关的制造与现有的CMOS晶体管制造工艺兼容。 通过掺杂悬臂并使用背偏压和金属悬臂尖，可以进一步提高开关的灵敏度。 纳米机电开关的占地面积可以小至0.1×0.1μm2。

公开(公告)号：US20160293737A1

公开(公告)日：2016-10-06

申请号：US14843221

申请日：2015-09-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66818 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/785

Abstract: A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.

Abstract translation: 公开了一种双宽度SOI FinFET，其中应变翅片的不同部分具有不同的宽度。 制造这种双宽度FinFET的方法需要使用湿化学蚀刻工艺横向凹入源极和漏极区域中的应变翅片，以便在修整源极中的鳍部的宽度的同时保持翅片中的高度应变 和漏极区域小于5nm。 所得的FinFET在栅极下方的沟道区域中具有鳍的宽部分，并且在源极和漏极区域中鳍的较窄部分。 较窄翅片的优点是在外延凸起的源极和漏极区域的生长期间可以更容易地掺杂。

公开(公告)号：US20160293602A1

公开(公告)日：2016-10-06

申请号：US14677404

申请日：2015-04-02

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L27/098 ,  H01L29/808 ,  H01L21/283 ,  H01L29/417 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66893 ,  H01L21/283 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/41791 ,  H01L29/66909 ,  H01L29/7832 ,  H01L29/8083

Abstract: A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

Abstract translation: 垂直结型场效应晶体管（JFET）由包括掺杂有第一导电型掺杂剂的半导体衬底内的源极区域的半导体衬底支撑。 掺杂有第一导电型掺杂剂的半导体材料的鳍具有与源极区域接触的第一端，并且还包括第二端和第二端之间的侧壁。 漏极区域由从鳍片的第二端生长并掺杂有第一导电型掺杂剂的第一外延材料形成。 栅极结构由从鳍的侧壁生长并掺杂有第二导电型掺杂剂的第二外延材料形成。