公开(公告)号：US09269815B2

公开(公告)日：2016-02-23

申请号：US14333135

申请日：2014-07-16

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/785

Abstract: One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin.

Abstract translation: 本文公开的一种方法包括在限定翅片的多个沟槽中形成共形衬垫层，在衬垫层上方形成绝缘材料层，暴露衬里层的部分，去除衬里层的部分，从而导致 大体呈U形的衬垫，位于每个沟槽的底部，对绝缘材料层进行至少一个第三蚀刻工艺，其中绝缘材料层的至少一部分位于U形的空腔内 衬垫层，并且在翅片周围形成栅极结构。 本文公开的FinFET器件包括限定翅片的多个沟槽，局部隔离，其包括大致U形的衬垫，其部分地限定腔体中定位的空腔和绝缘材料层，以及定位的门结构 围绕翅膀

公开(公告)号：US20160027700A1

公开(公告)日：2016-01-28

申请号：US14876212

申请日：2015-10-06

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Theodorus E. Standaert ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/417 ,  H01L21/311

CPC classification number: H01L21/823437 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785

Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

公开(公告)号：US09224811B2

公开(公告)日：2015-12-29

申请号：US14215398

申请日：2014-03-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/15

CPC classification number: H01L29/0673 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/155 ,  H01L29/42392 ,  H01L29/78696

Abstract: A stacked semiconductor device includes a first pair of vertically stacked self-aligned nanowires, a second pair of vertically stacked self-aligned nanowires, and a gate upon a semiconductor substrate, the gate surrounding portions of the first pair of vertically stacked self-aligned nanowires and the second pair of vertically stacked self-aligned nanowires. First epitaxy may merge the first pair of vertically stacked self-aligned nanowires and second epitaxy may merge second pair of vertically stacked self-aligned nanowires. The stacked semiconductor device may be fabricated by forming a lattice-fin upon the semiconductor substrate and the gate surrounding a portion of the lattice-fin. The vertically stacked self-aligned nanowires may be formed by selectively removing a plurality of layers from the lattice-fin.

Abstract translation: 堆叠的半导体器件包括第一对垂直堆叠的自对准纳米线，第二对垂直堆叠的自对准纳米线和半导体衬底上的栅极，第一对垂直堆叠的自对准纳米线的栅极周围部分 和第二对垂直堆叠的自对准纳米线。 第一外延可以合并第一对垂直堆叠的自对准纳米线，并且第二外延可以合并第二对垂直堆叠的自对准纳米线。 层叠的半导体器件可以通过在半导体衬底上形成晶格鳍并围绕晶格鳍的一部分形成栅极来制造。 垂直堆叠的自对准纳米线可以通过从晶格鳍选择性地去除多个层来形成。

公开(公告)号：US20150349083A1

公开(公告)日：2015-12-03

申请号：US14289737

申请日：2014-05-29

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/51 ,  H01L29/66 ,  H01L21/3213 ,  H01L49/02 ,  H01L21/02 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L23/535 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/285 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed includes, among other things, conformably depositing a layer of contact insulating material and a conductive material layer in a contact opening, forming a reduced-thickness sacrificial material layer in the contact opening so as to expose a portion, but not all, of the conductive material layer, removing portions of the conductive material layer and the layer of contact insulating material positioned above the upper surface of the reduced-thickness sacrificial material layer, removing the reduced-thickness sacrificial material layer, and forming a conductive contact in the contact opening that contacts the recessed portions of the conductive material layer and the layer of contact insulating material.

Abstract translation: 所公开的一种方法包括在接触开口中顺应地沉积接触绝缘材料层和导电材料层，在接触开口中形成减小厚度的牺牲材料层，以暴露部分，但不是全部， 的导电材料层的去除部分，去除部分导电材料层和接触绝缘材料层位于减薄厚度的牺牲材料层的上表面之上，去除减薄的牺牲材料层，并在其中形成导电接触 接触开口，其接触导电材料层的凹部和接触绝缘材料层。

公开(公告)号：US09196696B2

公开(公告)日：2015-11-24

申请号：US14260913

申请日：2014-04-24

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L23/48 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L29/4958 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/4966 ,  H01L29/66545

Abstract: Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, an integrated circuit includes a semiconductor substrate and a replacement metal gate structure overlying the semiconductor substrate. The replacement metal gate structure includes a first metal and a second metal and has a recess surface formed by the first metal and the second metal. The first metal and the second metal include a first species of diffused foreign ions. The integrated circuit further includes a metal fill material overlying the recess surface formed by the first metal and the second metal.

Abstract translation: 提供了具有改善的栅极均匀性的集成电路以及用于制造这种集成电路的方法。 在一个实施例中，集成电路包括覆盖半导体衬底的半导体衬底和替换金属栅极结构。 替代金属栅极结构包括第一金属和第二金属，并且具有由第一金属和第二金属形成的凹陷表面。 第一金属和第二金属包括扩散的外来离子的第一种。 集成电路还包括覆盖由第一金属和第二金属形成的凹陷表面的金属填充材料。

公开(公告)号：US09165836B1

公开(公告)日：2015-10-20

申请号：US14242046

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Michael Wedlake ,  Xiuyu Cai ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L21/70 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/28 ,  H01L21/321

CPC classification number: H01L27/088 ,  H01L21/28017 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7833

Abstract: One method disclosed includes, among other things, forming a gate registration structure above an isolation region, wherein the gate registration structure comprises a plurality of layers of material, the uppermost layer of which is a polish-stop layer, forming first and second sacrificial gate structures above first and second active regions, respectively, wherein the first and second sacrificial gate structures abut and engage opposite sides of the gate registration structure, and performing at least one first chemical mechanical polishing (CMP) process to remove the gate cap layer so as to thereby expose a sacrificial gate electrode in each of the first and second sacrificial gate structures, wherein the uppermost layer of the gate registration structure serves as a polish-stop layer during the at least one first CMP process.

Abstract translation: 公开的一种方法包括在隔离区域之上形成栅极配准结构，其中栅极配准结构包括多层材料，其最上层是抛光停止层，形成第一和第二牺牲栅极 分别在第一和第二有源区域之上的结构，其中第一和第二牺牲栅极结构邻接并接合栅极对准结构的相对侧，并且执行至少一个第一化学机械抛光（CMP）工艺以移除栅极盖层，以便 从而在第一和第二牺牲栅极结构中的每一个中露出牺牲栅电极，其中栅极配准结构的最上层在至少一个第一CMP工艺期间用作抛光停止层。

公开(公告)号：US20150279963A1

公开(公告)日：2015-10-01

申请号：US14226488

申请日：2014-03-26

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/324 ,  H01L29/49 ,  H01L21/223 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/66537 ,  H01L21/2236 ,  H01L21/324 ,  H01L27/0886 ,  H01L29/1083 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/785

Abstract: One method disclosed includes, among other things, covering a top surface and a portion of the sidewalls of a fin with etch stop material, forming a sacrificial gate structure above and around the fin, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one process operation to remove the sacrificial gate structure and thereby define a replacement gate cavity, forming a counter-doped region in the fin below an upper surface of the fin and below the channel region of the device, wherein the counter-doped region is doped with a second type of dopant material that is of an opposite type relative to the first type of dopant material, and forming a replacement gate structure in the replacement gate cavity.

Abstract translation: 公开的一种方法包括用蚀刻停止材料覆盖翅片的顶表面和一部分侧壁，在翅片上方和周围形成牺牲栅极结构，形成邻近牺牲栅极结构的侧壁间隔件， 至少一个处理操作以去除所述牺牲栅极结构，从而限定替换栅极腔，在所述鳍片的下表面以下且在所述器件的沟道区域下方形成鳍片中的反掺杂区域，其中所述反掺杂区域为 掺杂有相对于第一种掺杂剂材料相反类型的第二类型的掺杂剂材料，以及在替换栅极腔中形成替代栅极结构。

公开(公告)号：US20150255542A1

公开(公告)日：2015-09-10

申请号：US14200737

申请日：2014-03-07

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ajey P. Jacob ,  Witold P. Maszara

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, covering the top surface and a portion of the sidewalls of an initial fin structure with etch stop material, forming a sacrificial gate structure around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, removing the sacrificial gate structure, with the etch stop material in position, to thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the semiconductor substrate material of the fin structure positioned under the replacement gate cavity that is not covered by the etch stop material so as to thereby define a final fin structure and a channel cavity positioned below the final fin structure and substantially filling the channel cavity with a stressed material.

Abstract translation: 所公开的一种方法包括用蚀刻停止材料覆盖初始翅片结构的顶表面和侧壁的一部分，围绕初始翅片结构形成牺牲栅极结构，形成邻近牺牲栅极结构的侧壁间隔物， 去除牺牲栅极结构，其中蚀刻停止材料就位，从而限定替换栅极腔，通过替代栅极腔执行至少一个蚀刻工艺，以移除位于替换下方的鳍结构的半导体衬底材料的一部分 门腔不被蚀刻停止材料覆盖，从而限定最终的翅片结构和位于最终翅片结构下方的通道腔，并且用应力材料基本上填充通道腔。

公开(公告)号：US09093496B2

公开(公告)日：2015-07-28

申请号：US13945445

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Ajey P. Jacob ,  Kangguo Cheng ,  Bruce B. Doris ,  Nicolas Loubet ,  Prasanna Khare ,  Ramachandra Divakaruni

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/088 ,  H01L27/105 ,  H01L29/78 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L21/302

CPC classification number: H01L21/76243 ,  H01L21/302 ,  H01L21/76267 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/105 ,  H01L27/1211 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor fabrication methods are provided which include facilitating fabricating semiconductor fin structures by: providing a wafer with at least one fin extending above a substrate, the at least one fin including a first layer disposed above a second layer; mechanically stabilizing the first layer; removing at least a portion of the second layer of the fin(s) to create a void below the first layer; filling the void, at least partially, below the first layer with an isolation material to create an isolation layer within the fin(s); and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the fin(s), and a fin device(s) of a second architectural type in a second fin region of the fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供半导体制造方法，其包括通过以下方式制造半导体鳍片结构：提供具有在衬底上延伸的至少一个翅片的晶片，所述至少一个鳍片包括设置在第二层上方的第一层; 机械稳定第一层; 去除所述翅片的所述第二层的至少一部分以在所述第一层下面形成空隙; 至少部分地用隔离材料填充第一层下面的空隙，以在散热片内产生隔离层; 并且在翅片的第一翅片区域中形成第一结构类型的翅片装置，并且在翅片的第二翅片区域中形成第二结构类型的翅片装置， ，其中第一种架构类型和第二种架构类型是不同的鳍设备架构。

公开(公告)号：US08946793B2

公开(公告)日：2015-02-03

申请号：US13759209

申请日：2013-02-05

Applicant: Globalfoundries, Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/40 ,  H01L29/49

CPC classification number: H01L21/28114 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method of fabricating an integrated circuit includes forming an interlayer dielectric (ILD) layer over a dummy gate stack. The dummy gate stack includes a dummy gate structure, a hardmask layer, and sidewall spacers formed over a semiconductor substrate. The method further includes removing at least an upper portion of the dummy gate stack to form a first opening within the ILD layer, extending the first opening to form a first extended opening by completely removing the dummy gate structure of the dummy gate stack, and depositing at least one workfunction material layer within the first opening and within the first extended opening. Still further, the method includes removing portions of the workfunction material within the first opening and depositing a low-resistance material over remaining portions of the workfunction material thereby forming a replacement metal gate structure that includes the remaining portion of the workfunction material and the low-resistance material.

Abstract translation: 制造集成电路的方法包括在虚拟栅极堆叠上形成层间电介质（ILD）层。 虚拟栅极堆叠包括伪栅极结构，硬掩模层和形成在半导体衬底上的侧壁间隔物。 该方法还包括去除伪栅极堆叠的至少上部以在ILD层内形成第一开口，通过完全去除虚拟栅极堆叠的伪栅极结构，延伸第一开口以形成第一扩展开口，并且沉积 在所述第一开口内和所述第一延伸开口内的至少一个功函数材料层。 此外，该方法包括去除第一开口内的功函件材料的一部分，并在工作功能材料的剩余部分上沉积低电阻材料，从而形成包括功函件材料和低功能材料的剩余部分的替换金属栅结构， 电阻材料。