公开(公告)号：US11830817B2

公开(公告)日：2023-11-28

申请号：US17085215

申请日：2020-10-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Rahul Agarwal ,  Raja Swaminathan ,  Michael S. Alfano ,  Gabriel H. Loh ,  Alan D. Smith ,  Gabriel Wong ,  Michael Mantor

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/50 ,  H01L27/06

CPC classification number: H01L23/5384 ,  H01L21/50 ,  H01L23/5381 ,  H01L23/5385 ,  H01L25/0657 ,  H01L27/0688

Abstract: A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.

公开(公告)号：US20230376420A1

公开(公告)日：2023-11-23

申请号：US18302968

申请日：2023-04-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Susumu Mashimo ,  John Kalamatianos

IPC: G06F12/0862 ,  G06F12/0877 ,  G06F9/30 ,  G06F18/214

CPC classification number: G06F12/0862 ,  G06F12/0877 ,  G06F9/30047 ,  G06F9/30101 ,  G06F9/30036 ,  G06F18/214 ,  G06F2212/6024

Abstract: A method includes recording a first set of consecutive memory access deltas, where each of the consecutive memory access deltas represents a difference between two memory addresses accessed by an application, updating values in a prefetch training table based on the first set of memory access deltas, and predicting one or more memory addresses for prefetching responsive to a second set of consecutive memory access deltas and based on values in the prefetch training table.

公开(公告)号：US20230368832A1

公开(公告)日：2023-11-16

申请号：US18198709

申请日：2023-05-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G11C11/406 ,  G06F9/4401 ,  G06F1/3203

CPC classification number: G11C11/40611 ,  G06F9/442 ,  G06F1/3203 ,  G11C11/40615 ,  G06F9/4401

Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

公开(公告)号：US11809902B2

公开(公告)日：2023-11-07

申请号：US17031424

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexandru Dutu ,  Marcus Nathaniel Chow ,  Matthew D. Sinclair ,  Bradford M. Beckmann ,  David A. Wood

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F9/3838 ,  G06F9/545

Abstract: Techniques for executing workgroups are provided. The techniques include executing, for a first workgroup of a first kernel dispatch, a workgroup dependency instruction that includes an indication to prioritize execution of a second workgroup of a second kernel dispatch, and in response to the workgroup dependency instruction, dispatching the second workgroup of the second kernel dispatch prior to dispatching a third workgroup of the second kernel dispatch, wherein no workgroup dependency instruction including an indication to prioritize execution of the third workgroup has been executed.

公开(公告)号：US11809322B2

公开(公告)日：2023-11-07

申请号：US17472977

申请日：2021-09-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Amit P. Apte ,  Ganesh Balakrishnan ,  Eric Christopher Morton ,  Elizabeth M. Cooper ,  Ravindra N. Bhargava

IPC: G06F12/0817 ,  G06F12/128 ,  G06F12/0811 ,  G06F12/0871 ,  G06F12/0831

CPC classification number: G06F12/0817 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0871 ,  G06F12/128 ,  G06F2212/283 ,  G06F2212/604 ,  G06F2212/621

Abstract: Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Accordingly, the system includes a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system. The cache directory includes a reference count in each entry to track the aggregate number of cache lines that are cached per region. If a reference count of a given entry goes to zero, the cache directory reclaims the given entry.

公开(公告)号：US20230350484A1

公开(公告)日：2023-11-02

申请号：US18304849

申请日：2023-04-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Mihir Shaileshbhai Doctor ,  Alexander J. Branover ,  Benjamin Tsien ,  Indrani Paul ,  Christopher T. Weaver ,  Thomas J. Gibney ,  Stephen V. Kosonocky ,  John P. Petry

IPC: G06F1/3287 ,  G06F1/3296 ,  G06F1/3234

CPC classification number: G06F1/3287 ,  G06F1/3296 ,  G06F1/3278 ,  G06F1/3265

Abstract: A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component, and executes a process to exit the component from the reduced power state in response to the component being active.

公开(公告)号：US11805026B2

公开(公告)日：2023-10-31

申请号：US16993678

申请日：2020-08-14

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Stanley Ames Lackey, Jr. ,  Damon Tohidi ,  Gerald R. Talbot ,  Edoardo Prete

IPC: H04L41/147 ,  H04L43/50 ,  H04L43/0852 ,  H04L7/10 ,  H04L43/0823 ,  H04L25/14 ,  H04L7/06 ,  H04L7/00 ,  H04L7/04

CPC classification number: H04L41/147 ,  H04L7/06 ,  H04L7/10 ,  H04L25/14 ,  H04L43/0823 ,  H04L43/0852 ,  H04L43/50 ,  H04L7/0041 ,  H04L7/043

Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.

公开(公告)号：US11804479B2

公开(公告)日：2023-10-31

申请号：US16586309

申请日：2019-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Milind S. Bhagavat ,  Brett P. Wilkerson ,  Rahul Agarwal

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/0557 ,  H01L2224/08146

Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. A first semiconductor die has a second die stacked vertically on top of it in a three-dimensional integrated circuit. The first die includes a through silicon via (TSV) interconnect that does not traverse the first die. The first die includes one or more metal layers above the TSV, which connect to a bonding pad interface through a bonding pad via. If the signals transferred through the TSV of the first die are shared by the second die, then the second die includes a TSV aligned with the bonding pad interface of the first die. If these signals are not shared by the second die, then the second die includes an insulated portion of a wafer backside aligned with the bonding pad interface.

公开(公告)号：US11803734B2

公开(公告)日：2023-10-31

申请号：US15849617

申请日：2017-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel I. Lowell ,  Sergey Voronov ,  Mayank Daga

IPC: G06N3/063 ,  G06N3/08

CPC classification number: G06N3/063 ,  G06N3/08

Abstract: Methods, devices, systems, and instructions for adaptive quantization in an artificial neural network (ANN) calculate a distribution of ANN information; select a quantization function from a set of quantization functions based on the distribution; apply the quantization function to the ANN information to generate quantized ANN information; load the quantized ANN information into the ANN; and generate an output based on the quantized ANN information. Some examples recalculate the distribution of ANN information and reselect the quantization function from the set of quantization functions based on the resampled distribution if the output does not sufficiently correlate with a known correct output. In some examples, the ANN information includes a set of training data. In some examples, the ANN information includes a plurality of link weights.

公开(公告)号：US11803385B2

公开(公告)日：2023-10-31

申请号：US17548105

申请日：2021-12-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sateesh Lagudu ,  Arun Vaidyanathan Ananthanarayan ,  Michael Mantor ,  Allen H. Rush

IPC: G06F9/30 ,  G06F9/32 ,  G06F15/80 ,  G06F9/38 ,  G06T1/20

CPC classification number: G06F9/321 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3887 ,  G06F15/80 ,  G06T1/20

Abstract: An array processor includes processor element arrays (PEAs) distributed in rows and columns. The PEAs are configured to perform operations on parameter values. A first sequencer received a first direct memory access (DMA) instruction that includes a request to read data from at least one address in memory. A texture address (TA) engine requests the data from the memory based on the at least one address and a texture data (TD) engine provides the data to the PEAs. The PEAs provide first synchronization signals to the TD engine to indicate availability of registers for receiving the data. The TD engine provides second synchronization signals to the first sequencer in response to receiving acknowledgments that the PEAs have consumed the data.