公开(公告)号：US20230387121A1

公开(公告)日：2023-11-30

申请号：US18232670

申请日：2023-08-10

Applicant: Intel Corporation

Inventor： Joseph STEIGERWALD ,  Tahir GHANI ,  Oleg GOLONZKA

IPC: H01L27/092 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L21/768 ,  H01L23/485 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/41766 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002

Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.

公开(公告)号：US20230352561A1

公开(公告)日：2023-11-02

申请号：US18219986

申请日：2023-07-10

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Biswajeet GUHA ,  Tahir GHANI ,  Swaminathan SIVAKUMAR

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L21/306 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/02603 ,  H01L29/42392 ,  H01L29/66742 ,  H01L21/30604 ,  H01L21/02236 ,  H01L29/0673 ,  H01L29/78696 ,  H01L21/02532

Abstract: Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.

公开(公告)号：US20230317807A1

公开(公告)日：2023-10-05

申请号：US17693150

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  YenTing CHIU ,  David J. TOWNER ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having additive gate structures in a tub architecture are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric including a first dipole material layer. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric including a second dipole material layer. A dielectric wall is between and in contact with the P-type gate stack and the N-type gate stack.

公开(公告)号：US20230317788A1

公开(公告)日：2023-10-05

申请号：US17710837

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/0673 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/0847 ,  H01L29/1033

Abstract: Integrated circuit structures having full-wrap contact structures, and methods of fabricating integrated circuit structures having full-wrap contact structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. The conductive trench contact structure is electrically connected to a top of the epitaxial source or drain structure and to at least 10% of a length of each side of the epitaxial source or drain structure.

公开(公告)号：US20230317617A1

公开(公告)日：2023-10-05

申请号：US17710827

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE ,  Gurpreet SINGH

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76897

Abstract: Spacer self-aligned via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers protrudes above the plurality of gate structures and above the plurality of conductive trench contact structures. Individual ones of the plurality of dielectric spacers have an upper spacer portion on a lower spacer portion, with an interface between the upper spacer portion and the lower spacer portion.

公开(公告)号：US20230317595A1

公开(公告)日：2023-10-05

申请号：US17710817

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sukru YEMENICIOGLU ,  Makram ABD EL QADER ,  Tahir GHANI ,  Chanaka D. MUNASINGHE

IPC: H01L23/522 ,  H01L29/06 ,  H01L27/088 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L29/0673 ,  H01L27/0886 ,  H01L23/5283

Abstract: Integrated circuit structures having pre-epitaxial deep via structures, and methods of fabricating integrated circuit structures having pre-epitaxial deep via structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. A conductive via is vertically beneath and extends to the conductive trench contact structure. The conductive via has an uppermost surface above an uppermost surface of the epitaxial source or drain structure.

公开(公告)号：US20230207664A1

公开(公告)日：2023-06-29

申请号：US18116721

申请日：2023-03-02

Applicant: Intel Corporation

Inventor： Michael L. HATTENDORF ,  Curtis WARD ,  Heidi M. MEYER ,  Tahir GHANI ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H10B10/00 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

CPC classification number: H01L29/66545 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7843 ,  H01L27/0886 ,  H01L21/76232 ,  H01L29/6656 ,  H01L29/0653 ,  H01L21/823431 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L21/76816 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785 ,  H01L29/165 ,  H01L21/76846 ,  H01L21/76849 ,  H01L29/7845 ,  H01L21/76834 ,  H01L29/41791 ,  H01L21/76801 ,  H10B10/12 ,  H01L29/0649 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/0924 ,  H01L28/24 ,  H01L29/0847 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/7854 ,  H01L21/28518 ,  H01L23/5329 ,  H01L27/0207 ,  H01L28/20 ,  H01L29/41783 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823828 ,  H01L23/528 ,  H01L27/0922 ,  H01L29/167 ,  H01L29/66636 ,  H01L29/7851 ,  H01L21/76883 ,  H01L21/76885 ,  H01L29/665 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.

公开(公告)号：US20230178622A1

公开(公告)日：2023-06-08

申请号：US17544724

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Clifford ONG ,  Mohammad HASAN ,  Tahir GHANI ,  Charles H. WALLACE

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/66742 ,  H01L29/401

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a directed bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. A gate stack is over and around the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires, the second end opposite the first end, wherein at least one of the first or second epitaxial source or drain structures is coupled to fewer than all nanowires of the vertical arrangement of nanowires.

公开(公告)号：US20230154793A1

公开(公告)日：2023-05-18

申请号：US18098029

申请日：2023-01-17

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Tahir GHANI ,  Nadia M. RAHHAL-ORABI ,  Subhash M. JOSHI ,  Joseph M. STEIGERWALD ,  Jason W. KLAUS ,  Jack HWANG ,  Ryan MACKIEWICZ

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L21/285 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L29/785 ,  H01L21/76831 ,  H01L21/76849 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66477 ,  H01L29/517 ,  H01L29/78 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/518 ,  H01L29/665 ,  H01L29/16 ,  H01L29/456 ,  H01L21/28123 ,  H01L21/28562 ,  H01L23/535 ,  H01L2029/7858 ,  H01L29/495 ,  H01L2924/0002

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20230144607A1

公开(公告)日：2023-05-11

申请号：US18093776

申请日：2023-01-05

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Tahir GHANI ,  Atul MADHAVAN ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H10B10/00 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

CPC classification number: H01L29/66545 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7843 ,  H01L27/0886 ,  H01L21/76232 ,  H01L29/6656 ,  H01L29/0653 ,  H01L21/823431 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L21/76816 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785 ,  H01L29/165 ,  H01L21/76846 ,  H01L21/76849 ,  H01L29/7845 ,  H01L21/76834 ,  H01L29/41791 ,  H01L21/76801 ,  H10B10/12 ,  H01L29/0649 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/0924 ,  H01L28/24 ,  H01L29/0847 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/7854 ,  H01L21/28518 ,  H01L23/5329 ,  H01L27/0207 ,  H01L28/20 ,  H01L29/41783 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823828 ,  H01L23/528 ,  H01L27/0922 ,  H01L29/167 ,  H01L29/66636 ,  H01L29/7851 ,  H01L21/76883 ,  H01L21/76885 ,  H01L29/665 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.