公开(公告)号：US20120325910A1

公开(公告)日：2012-12-27

申请号：US13481459

申请日：2012-05-25

Applicant: Kenji Yoshida

Inventor： Kenji Yoshida

IPC: G06K19/00 ,  G06K7/10

CPC classification number: G06K19/06037 ,  G06K7/1417

Abstract: In exemplary embodiments, a dot pattern technique is provided with flexible length of data to be registered and with enhanced security by arranging a dot pattern to be disposed on a printed material, especially a block containing the dot pattern, on the basis of a new rule.

Abstract translation: 在示例性实施例中，点阵图案技术被提供有要登记的灵活长度的数据，并且通过基于新的规则，通过布置要布置在打印材料上的点图案，特别是包含点图案的块来设置增强的安全性 。

公开(公告)号：US20120324165A1

公开(公告)日：2012-12-20

申请号：US13404969

申请日：2012-02-24

Applicant: Norifumi Tsuboi ,  Kenji Yoshida

Inventor： Norifumi Tsuboi ,  Kenji Yoshida

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F11/1064

Abstract: According to one embodiment, a memory control device includes: a buffer memory; a cache memory performing caching for the buffer memory on a unit-data-by-unit-data basis; and an adding module adding ByteECC data to the unit data.

Abstract translation: 根据一个实施例，存储器控制装置包括：缓冲存储器; 高速缓冲存储器，以单位数据为单位数据进行缓冲存储器的缓存; 以及添加模块，将ByteECC数据添加到单元数据。

公开(公告)号：US20120199988A1

公开(公告)日：2012-08-09

申请号：US13501005

申请日：2010-10-13

Applicant: Toru Meura ,  Hiroki Nikaido ,  Kenzou Maejima ,  Yoji Ishimura ,  Kenji Yoshida

Inventor： Toru Meura ,  Hiroki Nikaido ,  Kenzou Maejima ,  Yoji Ishimura ,  Kenji Yoshida

IPC: H01L23/52 ,  H01L21/50

CPC classification number: H01L24/81 ,  C08L63/00 ,  C09D163/00 ,  H01L24/75 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13023 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/29191 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/7511 ,  H01L2224/75283 ,  H01L2224/7531 ,  H01L2224/7598 ,  H01L2224/81193 ,  H01L2224/81209 ,  H01L2224/8121 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83209 ,  H01L2224/83801 ,  H01L2224/83855 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Disclosed is a method of manufacturing an electronic device, that includes obtaining a stack of the first electronic component and the second electronic component, while placing a resin layer which contains a flux-active compound and a thermosetting resin, between the first terminals and the second terminals; bonding the first terminals and the second terminals with solder, by heating the stack at a temperature not lower than the melting point of solder layers on the first terminals, while pressurizing the stack using a fluid; and curing the resin layer. The duration from the point of time immediately after the start of heating of the stack, up to the point of time when the temperature of the stack reaches the melting point of the solder layers, is set to 5 seconds or longer, and 15 minutes or shorter.

Abstract translation: 公开了一种制造电子器件的方法，包括：在第一端子和第二端子之间放置包含助焊剂活性化合物和热固性树脂的树脂层，获得第一电子部件和第二电子部件的堆叠 终端; 通过在不低于第一端子处的焊料层的熔点的温度下加热堆叠，同时使用流体对堆叠进行加压，将焊料接合在第一端子和第二端子上; 并固化树脂层。 从堆叠的开始加热之后的时间点直到堆叠的温度达到焊料层的熔点的时间长度设定为5秒以上15分钟或 较短

公开(公告)号：US20120166148A1

公开(公告)日：2012-06-28

申请号：US13325742

申请日：2011-12-14

Applicant: Kenji Yoshida ,  Kisa Matsushima ,  Yoshine Ueda ,  Hiroaki Ishikawa

Inventor： Kenji Yoshida ,  Kisa Matsushima ,  Yoshine Ueda ,  Hiroaki Ishikawa

IPC: G06F17/50

CPC classification number: B64C3/14 ,  B64C30/00 ,  B64C2003/149 ,  B64F5/00 ,  G06F17/5095 ,  Y02T50/12

Abstract: In designing supersonic aircrafts, a method of designing a natural laminar flow wing is provided which reduces friction drag by delaying boundary layer transition under flight conditions of actual aircrafts. A target Cp distribution on wing upper surface, suited to natural laminarization in which boundary layer transition is delayed rearward in desired Reynolds number states, is defined by a functional type having as coefficients parameters depending on each spanwise station, a sensitivity analysis employing a transition analysis method is applied to the parameters, and a search is performed for the optimum combination of parameters to delay transition rearward.

Abstract translation: 在设计超音速飞机时，提供了一种设计自然层流翼的方法，通过延迟实际飞机飞行条件下的边界层过渡来减少摩擦阻力。 翼型上表面上的目标Cp分布适用于边界层转变在所需雷诺数状态下向后延伸的自然层流，由具有取决于每个翼展方向站的系数参数的函数类型定义，使用转换分析的灵敏度分析 方法应用于参数，并且对于参数的最佳组合执行搜索以向后延迟转换。

公开(公告)号：US08112167B2

公开(公告)日：2012-02-07

申请号：US12354574

申请日：2009-01-15

Applicant: Ayako Endo ,  Kenji Yoshida ,  Toshiya Kotani ,  Satoshi Tanaka

Inventor： Ayako Endo ,  Kenji Yoshida ,  Toshiya Kotani ,  Satoshi Tanaka

IPC: G06F19/00 ,  G06F17/50

CPC classification number: G05B19/41865 ,  G05B19/41885 ,  H01L22/20 ,  H01L2924/0002 ,  Y02P90/20 ,  Y02P90/26 ,  H01L2924/00

Abstract: A process control method comprises adjusting a process condition in consideration of a performance variation among a plurality of manufacturing apparatuses, the performance variation affecting a finished shape of a pattern used to manufacture a semiconductor device, running a simulation of the finished shape under the adjusted process condition, extracting a dangerous point of the pattern affecting satisfaction from the result of the simulation, comparing a first process capability serving as a judgment standard to find whether a production schedule of the device is achieved with a second capability serving to form a dangerous pattern containing the dangerous point, and improving the second process when the second process capability is lower than the first process capability.

Abstract translation: 一种过程控制方法包括考虑多个制造装置之间的性能变化来调整工艺条件，影响用于制造半导体器件的图案的成品形状的性能变化，在调整过程下运行成品形状的模拟 从模拟结果中提取影响满意度的模式的危险点，比较作为判断标准的第一处理能力，以确定是否实现具有第二能力的设备的生产计划，以形成含有 危险点，并且当第二处理能力低于第一处理能力时，改进第二过程。

公开(公告)号：US08086973B2

公开(公告)日：2011-12-27

申请号：US11958465

申请日：2007-12-18

Applicant: Kenji Yoshida ,  Soichi Inoue

Inventor： Kenji Yoshida ,  Soichi Inoue

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: A pattern management method includes extracting patterns having process margins equal to or below a predetermined value from a chip layout of an integrated circuit, screening a plurality of types of representative patterns from the extracted pattern, extracting patterns closest to the most outer periphery of the chip from the representative patterns, and representatively managing the extracted patterns which is closest to the most outer periphery of the chip.

Abstract translation: 图案管理方法包括从集成电路的芯片布局提取具有等于或低于预定值的处理余量的图案，从提取的图案中筛选多种类型的代表图案，提取最靠近芯片的最外周边的图案 并且代表性地管理最靠近芯片的最外围的提取图案。

公开(公告)号：US08078783B2

公开(公告)日：2011-12-13

申请号：US12319536

申请日：2009-01-08

Applicant: Kenji Yoshida

Inventor： Kenji Yoshida

IPC: H05K7/10

CPC classification number: G06F13/385

Abstract: An information processing apparatus includes a card slot to which a card-type medium is inserted, a determination unit configured to determine an operation mode, from among a first, second and third operation modes, which attains the highest speed of data communication between the information processing apparatus and the cardtype medium on the basis of a first, second and third communication speeds and the interruption-preventing maximum data size, and a data communication unit configured to perform data communication between the information processing apparatus and the card-type medium in the operation mode which attains the highest speed of the data communication and which is selected from among the first to third operation modes by the determination unit.

Abstract translation: 一种信息处理装置，包括插入卡型介质的卡槽，确定单元，被配置为从第一，第二和第三操作模式中确定操作模式，所述操作模式达到信息之间的最高数据通信速度 处理装置和卡式介质，基于第一，第二和第三通信速度和防止中断的最大数据大小，以及数据通信单元，被配置为在信息处理装置和卡型介质之间进行数据通信 操作模式，其通过确定单元达到数据通信的最高速度并且从第一至第三操作模式中选择。

公开(公告)号：US07996813B2

公开(公告)日：2011-08-09

申请号：US12654865

申请日：2010-01-07

Applicant: Masaaki Hatano ,  Motoya Okazaki ,  Junichi Wada ,  Takeshi Nishioka ,  Hisashi Kaneko ,  Takeshi Fujimaki ,  Kazuyuki Higashi ,  Kenji Yoshida ,  Noriaki Matsunaga

Inventor： Masaaki Hatano ,  Motoya Okazaki ,  Junichi Wada ,  Takeshi Nishioka ,  Hisashi Kaneko ,  Takeshi Fujimaki ,  Kazuyuki Higashi ,  Kenji Yoshida ,  Noriaki Matsunaga

IPC: G06F15/04

CPC classification number: G06F17/5068

Abstract: A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.

Abstract translation: 一种用于产生图案的方法包括：读出互连布局和孔布局;布置规定互连图案的布局布局;布置配置为连接到互连图案的孔图案的孔布局; 在图案处理区域中将在相同互连层级中连接的孔图案中的一个提取到所述互连图案之一; 提取包括所提取的孔图案的第一处理区域; 计算包括在第一处理区域中的互连图案的第一图案密度; 以及基于所述第一图案密度在所述第一处理区域中生成第一附加图案。

公开(公告)号：US07883824B2

公开(公告)日：2011-02-08

申请号：US12405710

申请日：2009-03-17

Applicant: Masafumi Asano ,  Kenji Yoshida ,  Masahiro Kanno

Inventor： Masafumi Asano ,  Kenji Yoshida ,  Masahiro Kanno

IPC: G03C5/00 ,  G03F9/00

CPC classification number: G03F7/70641 ,  G03F7/70625

Abstract: An evaluation method for lithography apparatus including a coating unit, an exposure unit, a heating unit and a development unit, the evaluation method including forming an evaluation resist pattern by using the lithography apparatus, the evaluation resist pattern including first and second evaluation patterns, the first and second evaluation patterns having different peripheral environments, measuring dimensions of the first and second evaluation patterns to obtain a dimensional difference between the first and second resist evaluation patterns, estimating an exposure dose of a resist when the resist is exposed by the exposure unit, the estimating the exposure dose being performed based on the dimensional difference between the first and second resist evaluation patterns, and estimating an effective heating temperature of the resist when the resist is heated by the heating unit, the estimating the effective heating temperature being performed based on the estimated exposure dose and the dimensional difference.

Abstract translation: 一种包括涂布单元，曝光单元，加热单元和显影单元的光刻设备的评估方法，所述评估方法包括通过使用光刻设备形成评估抗蚀剂图案，所述评估抗蚀剂图案包括第一和第二评估图案， 第一和第二评估图案具有不同的外围环境，测量第一和第二评估图案的尺寸以获得第一和第二抗蚀剂评估图案之间的尺寸差异，当抗蚀剂被曝光单元曝光时估计抗蚀剂的曝光剂量， 基于第一和第二抗蚀剂评估图案之间的尺寸差来估计正在进行的曝光剂量，以及当加热单元加热抗蚀剂时估计抗蚀剂的有效加热温度，基于 估计暴露剂量和t 他的尺寸差异。

公开(公告)号：US20110011940A1

公开(公告)日：2011-01-20

申请号：US12740278

申请日：2008-10-30

Applicant: Kenji Yoshida

Inventor： Kenji Yoshida

IPC: G06K19/06

CPC classification number: G06K19/06

Abstract: A dot pattern and a code pattern, a plurality of which can be printed on a small area, are provided. In the dot pattern, a first and a second dot patterns are superimposed and arranged. The first and the second dot patterns provide a plurality of reference dots in regions of blocks on which predetermined dots are arranged, arrange a plurality of virtual reference points defined by the reference dots, arrange information dots that define information by distances and directions from the virtual reference points, and further define at least orientations and sizes of the blocks based on arrangements of the reference dots as indexes of the blocks. The block is arranged so that part of or entire the reference dots and/or the virtual reference dots of the first and second dot patterns are superimposed together, and the number of the block is one, or a plurality of the blocks are repeatedly arranged in lateral and longitudinal directions.

Abstract translation: 提供了可以在小区域上印刷的多个点图案和码图案。 在点图案中，叠加并布置第一和第二点图案。 第一和第二点图案在其上布置有预定点的块区域中提供多个参考点，布置由参考点定义的多个虚拟参考点，根据虚拟的距离和方向布置定义信息的信息点 参考点，并且基于作为块的索引的参考点的布置来进一步限定块的至少取向和大小。 该块被布置成使得第一和第二点图案的参考点和/或虚拟参考点的一部分或全部被叠加在一起，并且块的数量是一个，或者多个块重复地布置在 横向和纵向。