公开(公告)号：US08907427B2

公开(公告)日：2014-12-09

申请号：US13668376

申请日：2012-11-05

Applicant: STMicroelectronics, Inc

Inventor： John H Zhang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/823807 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/7833

Abstract: A semiconductor device may include a substrate, source and drain regions in the substrate, a recessed epitaxial channel layer in the substrate between the source and drain regions, and a high-K gate dielectric layer overlying the recessed epitaxial channel layer. The semiconductor device may further include a gate electrode overlying the high-K gate dielectric layer, a dielectric cap layer in contact with top and sidewall portions of the gate electrode, the dielectric cap layer having a lower dielectric constant than the high-K gate dielectric layer, and source and drain contacts coupled to the source and drain regions.

Abstract translation: 半导体器件可以包括衬底，衬底中的源极和漏极区域，在源极和漏极区域之间的衬底中的凹陷的外延沟道层以及覆盖凹陷的外延沟道层的高K栅极电介质层。 半导体器件还可以包括覆盖高K栅极电介质层的栅电极，与栅电极的顶部和侧壁部分接触的电介质盖层，介电覆盖层具有比高K栅极电介质低的介电常数 层，以及耦合到源极和漏极区域的源极和漏极接触。

公开(公告)号：US08900973B2

公开(公告)日：2014-12-02

申请号：US13221198

申请日：2011-08-30

Applicant: Nathaniel C. Berliner ,  Pranita Kulkarni ,  Nicolas Loubet ,  Kingsuk Maitra ,  Sanjay C. Mehta ,  Paul A. Ronsheim ,  Toyoji Yamamoto ,  Zhengmao Zhu

Inventor： Nathaniel C. Berliner ,  Pranita Kulkarni ,  Nicolas Loubet ,  Kingsuk Maitra ,  Sanjay C. Mehta ,  Paul A. Ronsheim ,  Toyoji Yamamoto ,  Zhengmao Zhu

IPC: H01L21/326 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/7848

Abstract: A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.

Abstract translation: 制造半导体器件的方法在pFET区域中形成第一鳍，并且在nFET区域中形成第二鳍。 包含应变材料的多个保形微层沉积在第一和第二鳍片上。 在第一翅片上形成保护盖材料，并且从第二翅片选择性地去除保形层。 然后将应变材料热扩散到第一鳍中。 在热退火之后以及在从第二散热片选择性地去除保形微层之后，从第一散热片上去除保护帽材料。

公开(公告)号：US08877600B2

公开(公告)日：2014-11-04

申请号：US14104903

申请日：2013-12-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.A. ,  STMicroelectronics, Inc. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Claire Fenouillet-Beranger ,  Stephane Denorme ,  Nicolas Loubet ,  Qing Liu ,  Emmanuel Richard ,  Pierre Perreau

IPC: H01L21/20 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1207

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract translation: 一种制造混合SOI /体基板的方法，包括以下步骤：在绝缘层上在单晶半导体衬底上从包括称为SOI层的单晶半导体层的SOI晶片开始; 在SOI层上沉积至少一个掩模层，并形成与掩模层，SOI层和绝缘层交叉的开口，以到达衬底; 通过选择性外延和部分蚀刻步骤的重复交替生长半导体材料; 以及蚀刻围绕填充有半导体材料的所述开口的绝缘沟槽，同时在开口的周边向内侵入。

公开(公告)号：US20140312461A1

公开(公告)日：2014-10-23

申请号：US13866077

申请日：2013-04-19

Applicant: Commissariat A L'Energie Atomique Et Aux Energies Alternatives ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Laurent Grenouillet ,  Ali Khakifirooz ,  Yannick Le Tiec ,  Qing Liu ,  Maud Vinet

IPC: H01L21/761 ,  H01L29/06

CPC classification number: H01L21/2253 ,  H01L21/761 ,  H01L21/7624 ,  H01L21/76243 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0684 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Abstract translation: 用于半导体制造的方法包括在半导体衬底中形成阱。 在阱内形成一个口袋，该口袋具有与阱相反的掺杂极性，以在阱和口袋之间提供p-n结。 在p-n结处产生缺陷，使得p-n结的漏电阻减小。

公开(公告)号：US08860123B1

公开(公告)日：2014-10-14

申请号：US13852720

申请日：2013-03-28

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Prasanna Khare ,  Stephane Allegret-Maret ,  Nicolas Loubet ,  Qing Liu ,  Hemanth Jagannathan ,  Lisa Edge ,  Kangguo Cheng ,  Bruce Doris

IPC: H01L29/792 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

Abstract translation: 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域，以及栅极堆叠，其在沟道区域上具有第一介电层，在第一介电层上方具有第二介电层，第一扩散阻挡层 第一介电层，第一扩散阻挡层上的第一导电层，第一导电层上的第二扩散阻挡层，以及第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。

公开(公告)号：US08853843B2

公开(公告)日：2014-10-07

申请号：US13406681

申请日：2012-02-28

Applicant: Craig J. Rotay

Inventor： Craig J. Rotay

IPC: H01L27/00 ,  H01L23/32 ,  H01L25/11 ,  H01L23/00 ,  H01L23/66

CPC classification number: H01L25/115 ,  H01L23/32 ,  H01L23/562 ,  H01L23/66 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A semiconductor subassembly, a modular sidewall element having modular dimensions that accommodates placement of the semiconductor subassembly in a modular layout and a semiconductor substrate base element coupled to the modular sidewall element. The semiconductor substrate base element has at least one semiconductor element with a layout sized to be accommodated by modular dimensions of the modular sidewall element and the semiconductor substrate base element configured to form a base of the semiconductor subassembly.

Abstract translation: 半导体子组件，具有模块化尺寸的模块化侧壁元件，其适应半导体子组件在模块化布局中的放置以及耦合到模块化侧壁元件的半导体衬底基座元件。 半导体衬底基底元件具有至少一个半导体元件，其尺寸被设计成由模块化侧壁元件和半导体衬底基底元件的模块化尺寸来容纳，该半导体元件配置成形成半导体子组件的基座。

公开(公告)号：US08853832B2

公开(公告)日：2014-10-07

申请号：US12358015

申请日：2009-01-22

Applicant: Adalberto Cantoni

Inventor： Adalberto Cantoni

IPC: H01L23/552 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Mutual capacitances between regions of a MOS device become substantial factors that limit the speed and performance of the device as the device dimensions are reduced in size. A MOS transistor with a shielding structure formed above the gate is described. The shielding structure is connected to ground and is configured to reduce at least some of these mutual capacitances.

Abstract translation: MOS器件区域之间的互电容成为限制器件尺寸减小的器件的速度和性能的重要因素。 描述了形成在栅极上方的屏蔽结构的MOS晶体管。 屏蔽结构连接到地，并被配置为减少这些互电容中的至少一些。

公开(公告)号：US08853802B2

公开(公告)日：2014-10-07

申请号：US13485434

申请日：2012-05-31

Applicant: Venkatesh Mohanakrishnaswamy ,  Olivier Le Neel ,  Loi N. Nguyen

Inventor： Venkatesh Mohanakrishnaswamy ,  Olivier Le Neel ,  Loi N. Nguyen

IPC: H01L29/84 ,  H01L27/06 ,  B81C1/00

CPC classification number: H01L27/0617 ,  B81C1/00246 ,  B81C2203/0742 ,  H01L27/0611

Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.

Abstract translation: 提出了一种方法，其包括形成具有第一掺杂剂浓度的第一层，所述第一层具有集成电路区域和微机电区域，并且掺杂第一层的微机电区域以具有第二掺杂剂浓度。 该方法包括形成具有覆盖在第一层上的第三掺杂剂浓度的第二层，掺杂覆盖在微机电区域上的第二层以具有第四掺杂剂浓度，使用第一层形成微机电区域中的微机电结构 和第二层，并且使用第二层在集成电路区域中形成有源部件。

公开(公告)号：US20140291842A1

公开(公告)日：2014-10-02

申请号：US13853784

申请日：2013-03-29

Applicant: STMICROELECTRONICS, INC.

Inventor： Bernie Chrisanto ANG ,  Bryan Christian BACQUIAN

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A method of assembling a multi-chip electronic device into a thin electronic package entails inverting a flip-chip die arrangement over a hollow substrate, stacking additional dies on the hollow substrate to form a multi-chip electronic device, and encapsulating the multi-chip electronic device. Containment of the encapsulant can be achieved by joining split substrate portions, or by reinforcing a hollow unitary substrate, using a removable adhesive film. Use of the removable adhesive film facilitates surrounding the multi-chip electronic device with the encapsulant. The adhesive film can also prevent encapsulant from creeping around the substrate to an underside of the substrate that supports solder ball pads for subsequent attachment to a ball grid array (BGA) or a land grid array (LGA).

Abstract translation: 将多芯片电子器件组装成薄电子封装的方法需要在中空衬底上反转倒装芯片布置，在中空衬底上堆叠另外的管芯以形成多芯片电子器件，并且封装多芯片 电子设备。 密封剂的封闭可以通过使用可移除的粘合剂膜连接分离的衬底部分或通过加强中空的整体衬底来实现。 使用可移除的粘合膜有助于用密封剂围绕多芯片电子器件。 粘合剂膜还可以防止密封剂在衬底周围爬行到支撑焊球垫的衬底的下侧，用于随后附接到球栅阵列（BGA）或焊盘栅阵列（LGA）。

公开(公告)号：US08838953B2

公开(公告)日：2014-09-16

申请号：US12156832

申请日：2008-06-05

Applicant: Oleg Logvinov

Inventor： Oleg Logvinov

IPC: H04L29/06

CPC classification number: H04L63/065 ,  H04L63/18

Abstract: A provisioning device is provided that communicates over a trusted out-of-band communications channel to digital electronic devices in order to exchange security data such as passwords and private or public keys, thereby establishing a secure communications network between the devices.

Abstract translation: 提供了一种供应设备，其通过可信任的带外通信信道通信到数字电子设备，以便交换诸如密码和专用或公共密钥的安全数据，由此在设备之间建立安全的通信网络。