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公开(公告)号：US20170345836A1
公开(公告)日：2017-11-30
申请号：US15364603
申请日：2016-11-30
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Francesco La Rosa , Stephan Niel , Arnaud Regnier
IPC: H01L27/11531 , H01L29/788 , H01L29/66 , H01L27/11526 , H01L27/11521 , H01L21/28 , H01L21/266 , H01L21/265 , H01L29/861 , G11C16/04
CPC classification number: H01L27/11531 , G11C16/045 , H01L21/26513 , H01L21/266 , H01L21/28273 , H01L27/0629 , H01L27/0814 , H01L27/11521 , H01L27/11526 , H01L27/11536 , H01L27/1203 , H01L29/16 , H01L29/36 , H01L29/66136 , H01L29/66356 , H01L29/66825 , H01L29/7391 , H01L29/7394 , H01L29/788 , H01L29/861
Abstract: A method can be used to make a semiconductor device. A number of projecting regions are formed over a first semiconductor layer that has a first conductivity type. The first semiconductor layer is located on an insulating layer that overlies a semiconductor substrate. The projecting regions are spaced apart from each other. Using the projecting regions as an implantation mask, dopants having a second conductivity type are implanted into the first semiconductor layer, so as to form a sequence of PN junctions forming diodes in the first semiconductor layer. The diodes vertically extend from an upper surface of the first semiconductor layer to the insulating layer.
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公开(公告)号：US20170344310A1
公开(公告)日：2017-11-30
申请号：US15331470
申请日：2016-10-21
Inventor： Michael Peeters , Fabrice Marinet , Jean-Louis Modave , Fabrice Romain
CPC classification number: G06F3/0659 , G06F3/0611 , G06F3/064 , G06F3/0673 , G06F21/52 , G06F21/554 , G06F21/566 , G06F2221/034 , G09C1/00 , H04L9/004 , H04L2209/046 , H04L2209/12
Abstract: An algorithm execution method includes carrying out a first execution of the algorithm by a processing unit, sending at least one first result, which is to be written into a memory, to a memory management circuit, and storing said first result into a first area of the volatile memory. The method also includes carrying out a second execution of the algorithm by the processing unit, sending at least one second result, which is to be written into the memory, to the memory management circuit, and applying, by means of the memory management circuit, a different processing for the at least one second result in the second execution than was applied for the at least one first results in the first execution.
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公开(公告)号：US20170338824A1
公开(公告)日：2017-11-23
申请号：US15627157
申请日：2017-06-19
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre Sarafianos , Bruno Nicolas
IPC: H03K19/177 , H03K19/003 , H01L23/00
CPC classification number: H03K19/17768 , G06F21/75 , G06F21/87 , G09C1/00 , H01L23/576 , H03K19/0033 , H03K19/17704 , H04L9/004 , H04L2209/12
Abstract: An integrated circuit protection device, including: groups of radiation detection elements distributed in a matrix array; logic gates combining outputs of the detection elements in rows and in columns, each output of a detection element being connected to a gate combining a row and to a gate combining a column; and a circuit for interpreting signals supplied by said logic gates and including an event counter and a delay element.
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公开(公告)号：US20170324405A1
公开(公告)日：2017-11-09
申请号：US15361594
申请日：2016-11-28
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Albert Martinez , Michel Agoyan
IPC: H03K17/00 , H03K19/003 , H03K5/159
CPC classification number: H03K17/005 , G06F7/58 , H03K3/84 , H03K5/159 , H03K19/003 , H03K19/1737
Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.
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公开(公告)号：US20170301378A1
公开(公告)日：2017-10-19
申请号：US15363270
申请日：2016-11-29
Inventor： Francesco La Rosa , Gineuve Alieri
Abstract: A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.
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Patent Agency Ranking
公开(公告)号：US09792962B1
公开(公告)日：2017-10-17
申请号：US15363270
申请日：2016-11-29
Inventor： Francesco La Rosa , Gineuve Alieri
Abstract: A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.
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公开(公告)号：US09780045B2
公开(公告)日：2017-10-03
申请号：US15466396
申请日：2017-03-22
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Pascal Fornara , Christian Rivero , Guilhem Bouton
IPC: H01L23/00 , H01L27/02 , H01L21/768
CPC classification number: H01L23/576 , G06F17/5068 , H01L21/768 , H01L21/76838 , H01L23/573 , H01L27/0203 , H01L2924/0002 , H01L2924/00
Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.
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公开(公告)号：US09779815B2
公开(公告)日：2017-10-03
申请号：US15221318
申请日：2016-07-27
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet
IPC: G11C16/04 , G11C16/10 , G11C16/14 , H01L27/11521 , H01L29/788 , H01L27/11526
CPC classification number: G11C16/0408 , G11C16/0441 , G11C16/10 , G11C16/14 , H01L27/11521 , H01L27/11526 , H01L29/7883
Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.
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公开(公告)号：US20170278577A1
公开(公告)日：2017-09-28
申请号：US15365433
申请日：2016-11-30
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Francesco La Rosa , Stephan Niel , Arnaud Regnier
IPC: G11C16/34 , G11C16/26 , H01L29/788 , G11C16/08 , H01L27/115 , H01L29/792 , G11C16/04 , G11C16/10
CPC classification number: H01L29/7889 , G11C16/0433 , G11C16/0466 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3427 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L28/00 , H01L29/788 , H01L29/792
Abstract: The non-volatile memory device comprises memory cells each comprising a selectable state transistor having a floating gate and a control gate. The state transistor is of the depletion-mode type and is advantageously configured so as to have a threshold voltage that is preferably negative when the memory cell is in a virgin state. When the memory cell is read, a read voltage of zero may then be applied to the control gate and also to the control gates of the state transistors of all the memory cells of the memory device.
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公开(公告)号：US09753665B2
公开(公告)日：2017-09-05
申请号：US15053950
申请日：2016-02-25
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista
IPC: G06F3/06
CPC classification number: G06F3/0634 , G06F3/0604 , G06F3/0644 , G06F3/0688 , G11C5/066 , G11C7/10 , G11C8/12
Abstract: A memory device includes an input/output interface, a bus of SPI type coupled to the input/output interface, and a plurality of individual non-volatile memory devices connected to the bus of SPI type. The chip select inputs of each individual memory device are all connected to one and the same chip select wire of the SPI bus. The individual memory devices are further configured and controllable so as to behave, as seen by the input/output interface, as a single non-volatile memory device, the total memory space of which has a total memory capacity equal to the sum of the individual memory capacities of the individual devices.
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