公开(公告)号：US5841280A

公开(公告)日：1998-11-24

申请号：US881304

申请日：1997-06-24

Applicant: Gang Yu ,  Xiaoming Tang ,  Kurt-Martin Strack ,  Arthur Chuen Hon Cheng

Inventor： Gang Yu ,  Xiaoming Tang ,  Kurt-Martin Strack ,  Arthur Chuen Hon Cheng

IPC: G01V3/26 ,  G01V11/00 ,  G01V1/40 ,  G01V3/18

CPC classification number: G01V11/00 ,  G01V3/265

Abstract: A method for estimating porosity of an earth formation from measurements of acoustic energy traversing the earth formation and from measurements of seismoelectric voltages generated in the formation in response to the acoustic energy. The method includes the steps of measuring the acoustic energy traversing the earth formation and measuring said seismoelectric voltages generated in response to the acoustic energy traversing the formation. A seismoelectric signal is synthesized from the measurements of the acoustic energy using an initial value of the porosity. A difference is determined between the synthesized seismoelectric voltages and the measured seismoelectric voltages. The initial value of porosity is adjusted, and the steps of synthesizing the seismoelectric voltages from the acoustic signal, determining the difference, and adjusting the value of porosity are repeated until the difference drops below a predetermined threshold or the difference reaches a minimum value. The adjusted value of porosity which results in the difference being at the minimum is taken as the formation porosity. A particular embodiment includes estimating conductivity of fluid in the pore spaces of the formation by calculating the synthetic seismoelectric voltages using an initial value of conductivity; determining a difference between the synthetic seismoelectric voltages and the measured seismoelectric voltages; and adjusting the initial value of conductivity, and repeating the steps of calculating the synthetic seismoelectric voltages, determining the difference and adjusting the value of conductivity until the difference reaches a minimum.

Abstract translation: 一种通过对穿过地层的声能的测量以及响应于声能来测量在地层中产生的地震电压来估计地层的孔隙度的方法。 该方法包括以下步骤：测量穿过地层的声能，并测量响应于穿过地层的声能产生的地震电压。 使用孔隙率的初始值从声能的测量合成地震电信号。 在合成的地震电压和测量的地震电压之间确定差异。 调整孔隙率的初始值，并且重复从声信号合成地震电压，确定差值和调节孔隙度的步骤，直到该差降低到预定阈值以下或该差达到最小值。 导致差异最小的孔隙度的调整值作为地层孔隙度。 特定实施例包括使用电导率的初始值计算合成地震电压来估计地层孔隙空间中的流体的电导率; 确定合成地震电压和所测量的地震电压之间的差; 并调整电导率的初始值，并且重复计算合成地震电压的步骤，确定差值并调整电导率值，直到差达到最小值。

公开(公告)号：US5504323A

公开(公告)日：1996-04-02

申请号：US163174

申请日：1993-12-07

Applicant: Alan J. Heeger ,  Gang Yu

Inventor： Alan J. Heeger ,  Gang Yu

IPC: H01L33/00 ,  H01L51/30 ,  H01L51/50 ,  H01J40/14

CPC classification number: H01L51/5012 ,  H01L51/0038 ,  H01L51/4206 ,  H01L2251/308 ,  H01L51/0036 ,  H01L51/0041 ,  Y02E10/549

Abstract: Dual function diodes based on conjugated organic polymer active layers are disclosed. When positively biased the diodes function as light emitters. When negatively biased they are highly efficient photodiodes. Methods of preparation and use of these diodes in displays and input/output devices are also disclosed.

Abstract translation: 公开了基于共轭有机聚合物活性层的双功能二极管。 当正偏置时，二极管用作发光体。 当负偏压时，它们是高效光电二极管。 还公开了在显示器和输入/输出装置中制备和使用这些二极管的方法。

公开(公告)号：US20180108693A1

公开(公告)日：2018-04-19

申请号：US15296586

申请日：2016-10-18

Applicant: Chan-Long Shieh ,  Gang Yu ,  Guangming Wang

Inventor： Chan-Long Shieh ,  Gang Yu ,  Guangming Wang

IPC: H01L27/146

CPC classification number: H01L27/14616 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14658 ,  H01L27/14689 ,  H01L27/1469 ,  H01L27/14692

Abstract: A method of fabricating a structure including a high mobility backplane and a-Si photodiode imager includes forming a matrix of metal oxide thin film transistors on the surface of a rigid support member, depositing a planarizing layer on the matrix of transistors that is either porous or permissive/diffusive to oxygen at temperatures below approximately 200° C., and fabricating a matrix of passivated a-Si photodiodes over the matrix of transistors and electrically connected one each photodiode to each of the transistors. A continuous path is provided through the planarizing layer from the exterior of the structure to each of the transistors and the structure is annealed at a temperature below 200° C. in an oxygen ambient to move oxygen from the oxygen ambient to an active layer of each of the transistors and repair loss of oxygen damage to the transistors caused by the fabrication of the passivated a-Si photodiodes.

公开(公告)号：US09773918B2

公开(公告)日：2017-09-26

申请号：US14753460

申请日：2015-06-29

Applicant: Gang Yu ,  Chan-Long Shieh ,  Juergen Musolf ,  Fatt Foong ,  Tian Xiao

Inventor： Gang Yu ,  Chan-Long Shieh ,  Juergen Musolf ,  Fatt Foong ,  Tian Xiao

IPC: H01L29/786 ,  H01L21/02 ,  H01L23/31 ,  H01L23/29 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L21/02266 ,  H01L21/02269 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02565 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin film circuit includes a thin film transistor with a metal oxide semiconductor channel having a conduction band minimum (CBM) with a first energy level. The transistor further includes a layer of passivation material covering at least a portion of the metal oxide semiconductor channel. The passivation material has a conduction band minimum (CBM) with a second energy level. The second energy level being lower than, equal to, or no more than 0.5 eV above the first energy level. The circuit is used for an electronic device including any one of an AMLCD, AMOLED, AMLED, AMEPD.

公开(公告)号：US20170033202A1

公开(公告)日：2017-02-02

申请号：US15169356

申请日：2016-05-31

Applicant: Chan-Long Shieh ,  Gang Yu ,  Fatt Foong ,  Juergen Musolf

Inventor： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong ,  Juergen Musolf

IPC: H01L29/66 ,  H01L29/24 ,  H01L27/12 ,  H01L21/02 ,  H01L21/768 ,  H01L29/786 ,  H01L29/51

CPC classification number: H01L29/66969 ,  H01L21/02063 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76895 ,  H01L27/1225 ,  H01L29/247 ,  H01L29/42384 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2021/775

Abstract: A method of fabricating a stable high mobility amorphous MOTFT includes a step of providing a substrate with a gate formed thereon and a gate dielectric layer positioned over the gate. A carrier transport structure is deposited by sputtering on the gate dielectric layer. The carrier transport structure includes a layer of amorphous high mobility metal oxide adjacent the gate dielectric and a relatively inert protective layer of material deposited on the layer of amorphous high mobility metal oxide both deposited without oxygen and in situ. The layer of amorphous metal oxide has a mobility above 40 cm2/Vs and a carrier concentration in a range of approximately 1018 cm−3 to approximately 5×1019 cm−3. Source/drain contacts are positioned on the protective layer and in electrical contact therewith.

Abstract translation: 制造稳定的高迁移率无定形MOTFT的方法包括提供其上形成有栅极的基板和位于栅极上方的栅介质层的步骤。 通过溅射将载流子传输结构沉积在栅极介电层上。 载流子传输结构包括邻近栅极电介质的非晶高迁移率金属氧化物层，以及沉积在无氧和原位沉积的无定形高迁移率金属氧化物层上的相对惰性的材料保护层。 非晶金属氧化物层的迁移率高于40cm 2 / Vs，载流子浓度在约1018cm-3至约5×1019cm-3的范围内。 源极/漏极触点位于保护层上并与其电接触。

公开(公告)号：US20160247704A1

公开(公告)日：2016-08-25

申请号：US15143748

申请日：2016-05-02

Applicant: Chan-Long Shieh ,  Gang Yu

Inventor： Chan-Long Shieh ,  Gang Yu

IPC: H01L21/683 ,  H01L21/687 ,  H01L25/075 ,  H01L27/12 ,  H01L33/44 ,  H01L33/58 ,  H01L33/62 ,  H01L21/677 ,  H01L25/00

CPC classification number: H01L21/6836 ,  H01L21/67144 ,  H01L21/67721 ,  H01L21/68757 ,  H01L21/68778 ,  H01L25/042 ,  H01L25/0753 ,  H01L25/50 ,  H01L27/1222 ,  H01L27/1225 ,  H01L31/18 ,  H01L33/0095 ,  H01L33/44 ,  H01L33/58 ,  H01L33/62 ,  H01L2224/83 ,  H01L2224/95 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2933/0025 ,  H01L2933/0058 ,  H01L2933/0066 ,  Y10T156/171 ,  H01L2924/00

Abstract: A method of dispersing semiconductor chips from a wafer of semiconductor chips onto a substrate while preserving the neighboring relationship of each chip to each adjacent chip is disclosed. The method includes dispersing the wafer into sequential columns of semiconductor chips with a first pitch between columns while preserving the neighboring relationship and sequentially dispersing the columns of semiconductor chips into rows of individual chips with a second pitch between rows onto a substrate while preserving the neighboring relationship.

Abstract translation: 公开了将半导体芯片从半导体芯片的晶片分散到基板上同时保持每个芯片与每个相邻芯片的相邻关系的方法。 该方法包括将晶片分散在具有列之间的第一间距的顺序的半导体芯片列中，同时保持相邻关系，并将半导体芯片的列顺序地分散到具有行之间的第二间距的单个芯片行到基板上，同时保持相邻关系 。

公开(公告)号：US09401431B2

公开(公告)日：2016-07-26

申请号：US13366503

申请日：2012-02-06

Applicant: Chan-Long Shieh ,  Gang Yu

Inventor： Chan-Long Shieh ,  Gang Yu

IPC: H01L21/04 ,  H01L21/02 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78606

Abstract: A method of fabricating metal oxide TFTs on transparent substrates includes the steps of positioning an opaque gate metal area on the front surface of the substrate, depositing transparent gate dielectric and transparent metal oxide semiconductor layers overlying the gate metal and a surrounding area, depositing transparent passivation material on the semiconductor material, depositing photoresist on the passivation material, exposing and developing the photoresist to remove exposed portions, etching the passivation material to leave a passivation area defining a channel area, depositing transparent conductive material over the passivation area, depositing photoresist over the conductive material, exposing and developing the photoresist to remove unexposed portions, and etching the conductive material to leave source and drain areas on opposed sides of the channel area.

Abstract translation: 在透明基板上制造金属氧化物TFT的方法包括以下步骤：在衬底的前表面上定位不透明栅极金属区域，沉积覆盖栅极金属和周围区域的透明栅极电介质和透明金属氧化物半导体层，沉积透明钝化 在所述半导体材料上沉积光致抗蚀剂，在所述钝化材料上沉积光致抗蚀剂，曝光和显影所述光致抗蚀剂以去除暴露部分，蚀刻所述钝化材料以留下限定沟道区的钝化区，在所述钝化区上沉积透明导电材料， 导电材料，曝光和显影光致抗蚀剂以去除未曝光部分，并且蚀刻导电材料以在沟道区域的相对侧上留下源极和漏极区域。

公开(公告)号：US09397282B2

公开(公告)日：2016-07-19

申请号：US14620910

申请日：2015-02-12

Applicant: Chan-Long Shieh ,  Gang Yu

Inventor： Chan-Long Shieh ,  Gang Yu

IPC: H01L21/00 ,  H01L33/64 ,  H01L27/12 ,  H01L33/00 ,  H01L33/44 ,  H01L33/46 ,  H01L33/62 ,  H01L31/0368 ,  H01L27/146 ,  H01L31/0376 ,  H01L31/20

CPC classification number: H01L33/642 ,  H01L23/3677 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1262 ,  H01L27/1463 ,  H01L27/14663 ,  H01L27/14692 ,  H01L31/0368 ,  H01L31/0376 ,  H01L31/20 ,  H01L33/0075 ,  H01L33/44 ,  H01L33/46 ,  H01L33/62 ,  H01L2933/0025 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2933/0075

Abstract: A method of fabricating a pixelated projector display includes providing a wafer with a supporting substrate, a first semiconductive layer, an emission layer, and a second semiconductive layer. The wafer is patterned into an array of LEDs/LDs and a planarization layer is deposited over the array. One via for each LED/LD element is formed through the planarization layer. A MOTFT backplane is positioned on the planarization layer, one driver circuit in controlling electrical communication with each via through the planarization layer. A passivation layer is deposited over the MOTFT backplane and heat plugs are extended through the passivation layer, the MOTFT backplane, the planarization layer, and the III-V LED/LD wafer partially through the first semiconductive layer to thermally couple heat from the array of LEDs/LDs to the surface of the passivation layer. An upper end of the heat plugs is accessible for thermal coupling to a heat spreader and/or a heatsink.

Abstract translation: 制造像素化投影仪显示器的方法包括向晶片提供支撑衬底，第一半导体层，发射层和第二半导体层。 将晶片图案化成LED / LD阵列，并且平坦化层沉积在阵列上。 通过平坦化层形成每个LED / LD元件的一个通孔。 MFTFT背板位于平坦化层上，一个驱动电路通过平坦化层控制与每个通孔的电连通。 钝化层沉积在MOTFT背板上，并且热插塞通过钝化层，MOTFT背板，平坦化层和III-V LED / LD晶片部分延伸穿过第一半导体层，以热耦合来自 LED / LDs到钝化层的表面。 散热器和/或散热器的热连接可以接近热塞的上端。

公开(公告)号：US20160197139A1

公开(公告)日：2016-07-07

申请号：US15072744

申请日：2016-03-17

Applicant: Chan- Long Shieh ,  Gang Yu

Inventor： Chan- Long Shieh ,  Gang Yu

IPC: H01L29/04 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L29/04 ,  H01L21/00 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/16 ,  H01L21/28556 ,  H01L27/1214 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78693 ,  H01L51/5012

Abstract: A thin film semiconductor device has a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer.

公开(公告)号：US09331230B2

公开(公告)日：2016-05-03

申请号：US13663519

申请日：2012-10-30

Applicant: Chan-Long Shieh ,  Gang Yu

Inventor： Chan-Long Shieh ,  Gang Yu

IPC: H05K3/30 ,  H01L31/18 ,  H01L21/67 ,  H01L33/00 ,  H01L25/04 ,  H01L25/075

CPC classification number: H01L21/6836 ,  H01L21/67144 ,  H01L21/67721 ,  H01L21/68757 ,  H01L21/68778 ,  H01L25/042 ,  H01L25/0753 ,  H01L25/50 ,  H01L27/1222 ,  H01L27/1225 ,  H01L31/18 ,  H01L33/0095 ,  H01L33/44 ,  H01L33/58 ,  H01L33/62 ,  H01L2224/83 ,  H01L2224/95 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2933/0025 ,  H01L2933/0058 ,  H01L2933/0066 ,  Y10T156/171 ,  H01L2924/00

Abstract: A method of dispersing semiconductor chips from a wafer of semiconductor chips onto a substrate while preserving the neighboring relationship of each chip to each adjacent chip is disclosed. The method includes dispersing the wafer into sequential columns of semiconductor chips with a first pitch between columns while preserving the neighboring relationship and sequentially dispersing the columns of semiconductor chips into rows of individual chips with a second pitch between rows onto a substrate while preserving the neighboring relationship.

Abstract translation: 公开了将半导体芯片从半导体芯片的晶片分散到基板上同时保持每个芯片与每个相邻芯片的相邻关系的方法。 该方法包括将晶片分散在具有列之间的第一间距的顺序的半导体芯片列中，同时保持相邻关系，并将半导体芯片的列顺序地分散到具有行之间的第二间距的单个芯片行到基板上，同时保持相邻关系 。