公开(公告)号：US09633906B2

公开(公告)日：2017-04-25

申请号：US14162904

申请日：2014-01-24

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Theodorus E. Standaert ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L21/84 ,  H01L21/311 ,  H01L29/417

CPC classification number: H01L21/823437 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785

Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

公开(公告)号：US09627245B2

公开(公告)日：2017-04-18

申请号：US14197790

申请日：2014-03-05

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Nicolas Loubet

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/04 ,  H01L29/165

CPC classification number: H01L21/76224 ,  H01L29/045 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: One illustrative method disclosed herein involves, among other things, forming trenches to form an initial fin structure having an initial exposed height and sidewalls, forming a protection layer on at least the sidewalls of the initial fin structure, extending the depth of the trenches to thereby define an increased-height fin structure, with a layer of insulating material over-filling the final trenches and with the protection layer in position, performing a fin oxidation thermal anneal process to convert at least a portion of the increased-height fin structure into an isolation material, removing the protection layer, and performing an epitaxial deposition process to form a layer of semiconductor material on at least portions of the initial fin structure.

公开(公告)号：US20170084756A1

公开(公告)日：2017-03-23

申请号：US15202994

申请日：2016-07-06

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/265 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/26566 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

公开(公告)号：US09589848B2

公开(公告)日：2017-03-07

申请号：US14678024

申请日：2015-04-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Ghavam G. Shahidi

IPC: H01L21/027 ,  H01L21/205 ,  H01L21/308 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/20 ,  H01L21/033 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L21/3065 ,  H01L29/16

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/033 ,  H01L21/2018 ,  H01L21/2053 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

Abstract: Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer.

Abstract translation: 在半导体晶片或其它基板上形成硅和硅锗翅片，以便于产生紧密间隔的nFET和pFET器件。 在形成填充凹部的硅锗层的外延生长之前，使用图案化心轴层在晶片中形成一个或多个凹槽。 间隔件形成在图案化心轴层的侧壁上，随后移除心轴层。 蚀刻在间隔物之间​​的晶片和硅锗层的暴露区域以形成可用于来自晶片的nFET器件的鳍片和可用于来自硅锗层的pFET器件的鳍片。

公开(公告)号：US09589833B1

公开(公告)日：2017-03-07

申请号：US14850093

申请日：2015-09-10

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/423 ,  H01L21/768 ,  H01L29/06 ,  H01L23/535 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4991 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/66568

Abstract: Techniques for preventing leakage of contact material into air-gap spacers during contact formation. For example, a method comprises forming a contact trench on a semiconductor structure over an air-gap spacer and depositing a liner in the contact trench. The liner deposition material fills a portion of the air-gap spacer pinching off the contact trench to the air-gap spacer.

Abstract translation: 在接触形成期间防止接触材料泄漏到气隙间隔物中的技术。 例如，一种方法包括在气隙间隔物上的半导体结构上形成接触沟槽，并在接触沟槽中沉积衬垫。 衬垫沉积材料填充气隙间隔件的一部分，将接触沟槽夹紧到气隙间隔件。

公开(公告)号：US20170062590A1

公开(公告)日：2017-03-02

申请号：US15073065

申请日：2016-03-17

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L21/3086 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31 ,  H01L21/324 ,  H01L29/66795

Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etching process to remove a portion of the fin to cut the fin into a first cut fin and a second cut fin, the first cut fin having a first fin end and a second fin end and the second cut fin having a first fin end and a second fin end; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etching process to remove a portion of the second cut fin.

Abstract translation: 制造半导体器件的方法包括：在衬底中图形化翅片; 执行第一蚀刻工艺以去除所述翅片的一部分以将所述翅片切割成第一切割翅片和第二切割翅片，所述第一切割翅片具有第一翅片端部和第二翅片端部，所述第二切割翅片具有第一翅片 端和第二鳍末端; 沿着第一翅片端部的端壁和第一切割翅片的第二翅片端部的端壁以及第一翅片端部的端壁和第二切割翅片的第二翅片端部的端壁形成氧化物层; 将衬垫设置在设置在第一切割翅片的第一翅片端部的端壁上的氧化物层上以形成双层衬垫; 以及执行第二蚀刻工艺以去除所述第二切割翅片的一部分。

公开(公告)号：US20170062233A1

公开(公告)日：2017-03-02

申请号：US14841951

申请日：2015-09-01

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/31 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/16 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L21/3086 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31 ,  H01L21/324 ,  H01L29/66795

Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etching process to remove a portion of the fin to cut the fin into a first cut fin and a second cut fin, the first cut fin having a first fin end and a second fin end and the second cut fin having a first fin end and a second fin end; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etching process to remove a portion of the second cut fin.

公开(公告)号：US09583628B2

公开(公告)日：2017-02-28

申请号：US14558904

申请日：2014-12-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Douglas C. La Tulipe, Jr.

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/772 ,  H01L29/66 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/78603 ,  H01L29/0847 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78654

Abstract: A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate dielectric layer. Raised source/drain (RSD) regions are adjacent to the low-k spacers. The low-k spacers are embedded in an ILD on the RSD regions.

Abstract translation: 一种器件包括半导体衬底。 半导体衬底上的栅极叠层包括栅极介电层和栅极导体层。 低k间隔物与栅介质层相邻。 升高的源极/漏极（RSD）区域与低k间隔物相邻。 低k间隔物嵌入在RSD区域上的ILD中。

公开(公告)号：US09583597B2

公开(公告)日：2017-02-28

申请号：US13902540

申请日：2013-05-24

Applicant: GLOBALFOUNDRIES, Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L27/0886 ,  H01L29/785 ,  H01L29/7855

Abstract: Asymmetric FinFET devices and methods for fabricating such devices are provided. In one embodiment, a method includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon and depositing a conformal liner over the fin structures. A first portion of the conformal liner is removed, leaving a first space between the fins structures and forming a first metal gate in the first space between the fin structures. A second portion of the conformal liner is removed, leaving a second space between the fin structures and forming a second metal gate in the second space between the fin structures.

Abstract translation: 提供非对称FinFET器件及其制造方法。 在一个实施例中，一种方法包括提供包括形成在其上的多个翅片结构的半导体衬底，并且在翅片结构上沉积保形衬垫。 去除保形衬套的第一部分，在翅片结构之间留下第一空间，并在翅片结构之间的第一空间中形成第一金属浇口。 去除保形衬套的第二部分，在翅片结构之间留下第二空间，并在翅片结构之间的第二空间中形成第二金属浇口。

公开(公告)号：US09564486B2

公开(公告)日：2017-02-07

申请号：US14839378

申请日：2015-08-28

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  RENESAS ELECTRONICS CORPORATION

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract translation: 形成半导体结构的方法包括在第一组鳍片的翅片之间以及在第二组鳍片的翅片之间形成第一隔离区域。 第一组翅片形成在体半导体衬底中。 第二隔离区域形成在第一散热片组和第二散热片组之间，第二隔离区域延伸穿过第一隔离区域的一部分，使得第一隔离区域和第二隔离区域直接接触并且高于主体 第二隔离区域的半导体衬底大于第一隔离区域的体半导体衬底上方的高度。