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    SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES
    245.
    发明申请
    SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES 审中-公开
    具有更换门结构的半导体器件

    公开(公告)号：US20160093713A1

    公开(公告)日：2016-03-31

    申请号：US14963378

    申请日：2015-12-09

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei ,  Qi Zhang ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

    IPC: H01L29/51 ,  H01L29/78

    CPC classification number: H01L29/513 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

    Abstract: A transistor device includes a semiconductor substrate and a gate structure positioned above a surface of the semiconductor substrate. The gate structure includes a high-k gate insulation layer positioned above the surface of the semiconductor substrate and at least one work-function adjusting layer of material positioned above the high-k gate insulation layer, wherein an upper surface of the at least one work-function adjusting layer of material has a stepped profile when viewed in cross-section taken in a gate-width direction of the transistor device. The gate structure further includes a layer of conductive material positioned on the stepped upper surface of the at least one work-function adjusting layer of material.

    Abstract translation: 晶体管器件包括半导体衬底和位于半导体衬底表面之上的栅极结构。 栅极结构包括位于半导体衬底的表面上方的高k栅极绝缘层和位于高k栅极绝缘层上方的材料的至少一个功函数调节层，其中该至少一个工件的上表面 当在晶体管器件的栅极宽度方向上截取的横截面中观察时，材料的功能调节层具有阶梯形轮廓。 栅极结构还包括位于至少一个功函数调节层材料的阶梯状上表面上的导电材料层。

    METHODS OF FORMING CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
    246.
    发明申请
    METHODS OF FORMING CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES 有权
    形成半导体器件和结果器件的接触结构的方法

    公开(公告)号：US20160049332A1

    公开(公告)日：2016-02-18

    申请号：US14457708

    申请日：2014-08-12

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Vimal Kamineni ,  William J. Taylor, JR.

    IPC: H01L21/768 ,  H01L23/535

    CPC classification number: H01L29/4975 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/535 ,  H01L29/41758 ,  H01L29/78 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One method disclosed herein includes, among other things, a method of forming a contact structure to a source/drain region of a transistor device. The transistor device includes a gate structure and a gate cap layer positioned above the gate structure. The method includes forming an extended-height epi contact structure that is conductively coupled to the source/drain region. The extended-height epi contact structure includes an upper surface that is positioned at a height level that is above a height level of an upper surface of the gate cap layer. The method further includes performing an etching process to trim at least a lateral width of a portion of the extended-height epi contact structure, and, after performing the etching process, forming a metal silicide material on at least a portion of the trimmed extended-height epi contact structure and forming a conductive contact on the metal silicide material.

    Abstract translation: 本文公开的一种方法包括形成与晶体管器件的源极/漏极区域的接触结构的方法。 晶体管器件包括栅极结构和位于栅极结构上方的栅极帽层。 该方法包括形成导电耦合到源极/漏极区的扩展高度外延接触结构。 所述延伸高度外延接触结构包括位于所述栅极盖层的上表面的高度以上的高度水平处的上表面。 该方法还包括执行蚀刻工艺以修剪延伸高度外延接触结构的一部分的至少横向宽度，并且在执行蚀刻工艺之后，在修剪的延伸高度外延接触结构的至少一部分上形成金属硅化物材料， 高度epi接触结构，并在金属硅化物材料上形成导电接触。

    FinFET semiconductor devices with local isolation features and methods for fabricating the same
    247.
    发明授权
    FinFET semiconductor devices with local isolation features and methods for fabricating the same 有权
    具有局部隔离特性的FinFET半导体器件及其制造方法

    公开(公告)号：US09245979B2

    公开(公告)日：2016-01-26

    申请号：US13902369

    申请日：2013-05-24

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Songkram Srivathanakul

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/66795 ,  H01L29/7851

    Abstract: FinFET semiconductor devices with local isolation features and methods for fabricating such devices are provided. In one embodiment, a method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon, wherein each of the plurality of fin structures has sidewalls, forming spacers about the sidewalls of the plurality of fin structures, and forming a silicon-containing layer over the semiconductor substrate and in between the plurality of fin structures. The method further includes removing at least a first portion of the silicon-containing layer to form a plurality of void regions while leaving at least a second portion thereof in place and depositing an isolation material in the plurality of void regions.

    Abstract translation: 提供具有局部隔离特征的FinFET半导体器件和用于制造这种器件的方法。 在一个实施例中，制造半导体器件的方法包括提供包括形成在其上的多个翅片结构的半导体衬底，其中，所述多个翅片结构中的每一个具有侧壁，围绕所述多个翅片结构的侧壁形成间隔件，以及形成 位于所述半导体衬底上并位于所述多个翅片结构之间的含硅层。 该方法还包括移除含硅层的至少第一部分以形成多个空隙区域，同时至少留下第二部分，并在多个空隙区域中沉积隔离材料。

    Methods of forming lateral and vertical FinFET devices and the resulting product
    248.
    发明授权
    Methods of forming lateral and vertical FinFET devices and the resulting product 有权
    形成横向和垂直FinFET器件和所得产品的方法

    公开(公告)号：US09245885B1

    公开(公告)日：2016-01-26

    申请号：US14674656

    申请日：2015-03-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Andreas Knorr

    IPC: H01L21/336 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

    CPC classification number: H01L29/7827 ,  H01L21/823431 ,  H01L21/823487 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858

    Abstract: One illustrative method disclosed herein includes, among other things, forming first and second recessed gate structures, recessing the second recessed gate structure so as to define a further recessed second gate structure that exposes a channel structure within a gate cavity, forming first and second gate cap layers in first and second replacement gate cavities, respectively, forming a recess in the second gate cap layer that exposes the channel structure, forming a semiconductor material on the exposed portion of the channel structure within the recess in the second gate cap layer so as to define a first source/drain region for the vertical FinFET device, and forming various contact structures to the gates of the devices and the first source/drain region.

    Abstract translation: 本文公开的一种说明性方法包括形成第一和第二凹陷栅极结构，凹陷第二凹陷栅极结构以便限定暴露栅极腔内的沟道结构的另外凹陷的第二栅极结构，形成第一和第二栅极 分别在第一和第二替换栅极腔中形成盖层，在第二栅极盖层中形成露出沟道结构的凹槽，在第二栅极盖层的凹槽内的沟道结构的暴露部分上形成半导体材料，以便 以限定用于垂直FinFET器件的第一源极/漏极区域，以及向器件和第一源极/漏极区域的栅极形成各种接触结构。

    Methods of forming finFET semiconductor devices using a replacement gate technique and the resulting devices
    249.
    发明授权
    Methods of forming finFET semiconductor devices using a replacement gate technique and the resulting devices 有权
    使用替代栅极技术形成finFET半导体器件的方法和所得到的器件

    公开(公告)号：US09236480B2

    公开(公告)日：2016-01-12

    申请号：US14044120

    申请日：2013-10-02

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC: H01L29/78 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

    CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

    Abstract: One method disclosed includes, among other things, forming a raised isolation post structure between first and second fins, wherein the raised isolation post structure partially defines first and second spaces between the first and second fins, respectively, and forming a gate structure around the first and second fins and the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces. One illustrative device includes, among other things, first and second fins, a raised isolation post structure positioned between the first and second fins, first and second spaces defined by the fins and the raised isolation post structure, and a gate structure positioned around a portion of the fins and the isolation post structure.

    Abstract translation: 所公开的一种方法包括在第一和第二散热片之间形成凸起的隔离柱结构，其中所述凸起的隔离柱结构分别部分地限定所述第一和第二鳍之间的第一和第二空间，并且形成围绕所述第一和第二鳍的栅极结构 和第二鳍片和凸起的隔离柱结构，其中栅极结构的至少一部分位于第一和第二空间中。 一个说明性装置尤其包括第一和第二散热片，位于第一和第二散热片之间的凸起的隔离柱结构，由翅片和凸起的隔离柱结构限定的第一和第二空间以及围绕一部分 的翅片和隔离柱结构。

    FORMING GATE AND SOURCE/DRAIN CONTACT OPENINGS BY PERFORMING A COMMON ETCH PATTERNING PROCESS
    250.
    发明申请
    FORMING GATE AND SOURCE/DRAIN CONTACT OPENINGS BY PERFORMING A COMMON ETCH PATTERNING PROCESS 有权
    通过执行常见蚀刻过程形成门和源/排水接触开口

    公开(公告)号：US20150364378A1

    公开(公告)日：2015-12-17

    申请号：US14301748

    申请日：2014-06-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  William J. Taylor, JR. ,  Min Gyu Sung

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/28

    CPC classification number: H01L29/41783 ,  H01L21/28008 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/088 ,  H01L29/0653

    Abstract: One method disclosed herein includes forming an opening in a layer of material so as to expose the source/drain regions of a transistor and a first portion of a gate cap layer positioned above an active region, reducing the thickness of a portion of the gate cap layer positioned above the isolation region, defining separate initial source/drain contacts positioned on opposite sides of the gate structure, performing a common etching process sequence to define a gate contact opening that extends through the reduced-thickness portion of the gate cap layer and a plurality of separate source/drain contact openings in the layer of insulating material, and forming a conductive gate contact structure and conductive source/drain contact structures.

    Abstract translation: 本文公开的一种方法包括在材料层中形成开口以暴露晶体管的源极/漏极区域和位于有源区域上方的栅极覆盖层的第一部分，从而减小栅极帽部分的厚度 位于隔离区域上方的层，限定位于栅极结构的相对侧上的单独的初始源极/漏极触点，执行公共蚀刻工艺序列以限定延伸穿过栅极盖层的厚度减小的部分的栅极接触开口，以及 绝缘材料层中的多个独立的源极/漏极接触开口，以及形成导电栅极接触结构和导电源极/漏极接触结构。

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