公开(公告)号：US10269983B2

公开(公告)日：2019-04-23

申请号：US15590409

申请日：2017-05-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Hui Zang ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/12 ,  H01L29/41

Abstract: Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A fin is formed that includes a first nanosheet channel layer and a second nanosheet channel layer arranged in a vertical stack. A cavity is formed between a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer. An epitaxially-grown source/drain region is connected with the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer. A gate structure is formed that includes a section located in a space between the first nanosheet channel layer and the second nanosheet channel layer. The cavity is surrounded by the first nanosheet channel layer, the second nanosheet channel layer, the section of the gate structure, and the source/drain region to define an air gap spacer.

公开(公告)号：US10263151B2

公开(公告)日：2019-04-16

申请号：US15680977

申请日：2017-08-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey P. Jacob ,  Srinivasa Banna ,  Deepak Nayak

IPC: H01L27/15 ,  H01L33/24 ,  H01L33/40 ,  H01L21/20 ,  H01L33/18 ,  H01L33/38 ,  H01L33/06 ,  H01L33/32 ,  H01L33/00 ,  H01L33/12 ,  H01L33/46 ,  H01L33/36 ,  H01L33/16

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diodes and methods of manufacture. The method includes: forming fin structures with a doped core region, on a substrate material; forming a first color emitting region by cladding the doped core region of a first fin structure of the fin structures, while protecting the doped core regions of a second fin structure and a third fin structure of the fin structures; forming a second color emitting region by cladding the doped core region of the second fin structure, while protecting the doped core regions of the first fin structure and the third fin structure; and forming a third color emitting region by cladding the doped core region of the third fin structure, while protecting the doped core regions of the first fin structure and the second fin structure.

公开(公告)号：US10263099B2

公开(公告)日：2019-04-16

申请号：US15876606

申请日：2018-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/22 ,  H01L29/49 ,  H01L29/51

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US10263013B2

公开(公告)日：2019-04-16

申请号：US15441711

申请日：2017-02-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/84 ,  H01L49/02 ,  H01L21/265 ,  H01L29/08 ,  H01L29/45 ,  H01L27/06 ,  H01L29/06

Abstract: Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions. Also disclosed is an IC structure formed using the method.

公开(公告)号：US10262941B2

公开(公告)日：2019-04-16

申请号：US15136384

申请日：2016-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason Eugene Stephens ,  Tuhin Guha Neogi ,  Kai Sun ,  Deniz Elizabeth Civay ,  David Charles Pritchard ,  Andy Wei

IPC: H01L21/33 ,  H01L23/528 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20190108873A1

公开(公告)日：2019-04-11

申请号：US15729067

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Hui Zang ,  Josef Watts

IPC: G11C11/419 ,  G11C11/418 ,  H01L27/11 ,  H01L29/78 ,  G11C11/412 ,  H01L21/8238

Abstract: Integrated circuits including a static random access memory (SRAM) cell, methods of operating the same, and methods of fabricating the same are provided herein. In an embodiment, an integrated circuit includes the SRAM cell. The SRAM cell includes a first pass-gate transistor and a second pass-gate transistor. The SRAM cell further includes a first word line and a second word line. The first word line and the second word line are electrically independent of each other. The first pass-gate transistor and/or the second pass-gate transistor include a first gate in electrical communication with the first word line and a second gate in electrical communication with the second word line with the first gate and the second gate included in the same pass-gate transistor.

公开(公告)号：US20190107672A1

公开(公告)日：2019-04-11

申请号：US15725524

申请日：2017-10-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey P. JACOB

IPC: G02B6/122 ,  G02B6/132

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to non-planar waveguide structures and methods of manufacture. The waveguide structure includes: non-planar structures composed of a first material; a cladding layer over the non-planar structures composed of a second material; and a material formed over the cladding layer.

公开(公告)号：US10256089B2

公开(公告)日：2019-04-09

申请号：US15626732

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Haigou Huang ,  Jinsheng Gao ,  Tai Fong Chao

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/768 ,  H01L21/28

Abstract: Interconnect structures and methods of forming an interconnect structure. A sacrificial contact is arranged between a first gate structure and a second gate structure. The sacrificial contact extends vertically to a source/drain region. A section of the sacrificial contact is removed to form a cut opening extending vertically to the source/drain region. A first dielectric layer is deposited in the cut opening, and is then partially removed to open a space in the cut opening that is arranged vertically above the first dielectric layer. A second dielectric layer is deposited that fills the space in the cut opening and forms a cap on the first dielectric layer. The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

公开(公告)号：US10255987B1

公开(公告)日：2019-04-09

申请号：US15730107

申请日：2017-10-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. Fifield

IPC: G11C29/12 ,  G11C29/50

Abstract: The present disclosure relates to a structure which includes a current-mirror control node which is configured to adjust a current margin and provide the adjusted current margin to at least one one-time programmable memory (OTPM) cell.

公开(公告)号：US20190101905A1

公开(公告)日：2019-04-04

申请号：US15719680

申请日：2017-09-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongxin Zhang ,  Shaowen Gao ,  Norman Chen

IPC: G05B19/418

CPC classification number: G05B19/41845 ,  G05B2219/36089 ,  G05B2219/45031

Abstract: Methods according to the disclosure include: converting an image of a manufactured circuit to a plurality of representative contours, the plurality of representative contours corresponding to printed features in the manufactured circuit; generating a risk inventory for the manufactured circuit based on the plurality of representative contours, the risk inventory being configured to identify at least one process sensitive geometry (PSG) in the manufactured circuit; generating a common process window (CPW) for the manufactured circuit based on the plurality of representative contours and the risk inventory, the CPW being indicative of manufacturing reliability of each feature in the manufactured circuit; and generating instructions to adjust a manufacturing tool for creating the manufactured circuit, based on the generated CPW.