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公开(公告)号：US09838134B1
公开(公告)日：2017-12-05
申请号：US14984849
申请日：2015-12-30
Applicant: INPHI CORPORATION
Inventor： Todd Rope , Radhakrishnan L. Nagarajan , Hari Shankar
IPC: G02F1/01 , H04B10/516
CPC classification number: H04B10/516 , G02F1/0123 , G02F1/0147 , G02F1/025 , G02F1/225 , G02F1/2255 , G02F2001/212 , G02F2202/105 , H01S3/06754 , H01S5/0085 , H01S5/0687 , H01S5/4012 , H01S5/4087 , H04B10/505 , H04B10/50575
Abstract: The present invention relates to telecommunication techniques and integrated circuit (IC) devices. More specifically, embodiments of the present invention provide an off-quadrature modulation system. Once an off-quadrature modulation position is determined, a ratio between DC power transfer amplitude and dither tone amplitude for a modulator is as a control loop target to stabilize off-quadrature modulation. DC power transfer amplitude is obtained by measuring and sampling the output of an optical modulator. Dither tone amplitude is obtained by measuring and sampling the modulator output and performing calculation using the optical modulator output values and corresponding dither tone values. There are other embodiments as well.
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公开(公告)号：US09817610B1
公开(公告)日：2017-11-14
申请号：US14963148
申请日：2015-12-08
Applicant: INPHI CORPORATION
Inventor： Aws Shallal , Dan Kunkel
CPC classification number: G06F12/0246 , G06F11/14 , G06F12/0238 , G06F12/0804 , G06F12/0868 , G06F13/16 , G06F2212/1024 , G06F2212/1032 , G06F2212/1056 , G06F2212/214 , G06F2212/313
Abstract: An apparatus forms a memory system that is physically populated into a host. In a powered-on state, the apparatus logically connects to the host through a host memory controller configured to receive host-initiated commands. The memory system includes a command buffer coupled to the host memory controller to receive the host-initiated commands. The memory system comprises both volatile memory (e.g., RAM) and non-volatile memory (e.g., FLASH). A non-volatile memory controller (NVC) is coupled to the volatile memory, and is also coupled to the non-volatile memory. A command sequence processor that is co-resident with the NVC responds to a trigger signal by logically disconnecting from the host, then dispatching command sequences that perform successive read/write operations between the volatile memory and the non-volatile memory. The successive read/write operations are performed even when the host is in a powered-down state.
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公开(公告)号：US09787423B2
公开(公告)日：2017-10-10
申请号：US15375031
申请日：2016-12-09
Applicant: INPHI CORPORATION
Inventor： Radhakrishnan L. Nagarajan
Abstract: An integrated apparatus with optical/electrical interfaces and protocol converter on a single silicon substrate. The apparatus includes an optical module comprising one or more modulators respectively coupled with one or more laser devices for producing a first optical signal to an optical interface and one or more photodetectors for detecting a second optical signal from the optical interface to generate a current signal. Additionally, the apparatus includes a transmit lane module coupled between the optical module and an electrical interface to receive a first electric signal from the electrical interface and provide a framing protocol for driving the one or more modulators. Furthermore, the apparatus includes a receive lane module coupled between the optical module and the electrical interface to process the current signal to send a second electric signal to the electrical interface.
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公开(公告)号：US09746744B1
公开(公告)日：2017-08-29
申请号：US15609655
申请日：2017-05-31
Applicant: INPHI CORPORATION
Inventor： Jie Lin , Masaki Kato , Robb Johnson
CPC classification number: G02F1/2257 , G02B6/134 , G02B6/136 , G02B2006/12061 , G02B2006/12142 , G02B2006/12173 , G02F2001/212
Abstract: A method of forming a waveguide for a self-aligned Mach-Zehnder-Interferometer. The method includes forming a waveguide on a substrate and providing a first mask with a first opening exposing a first width and a pair of second widths towards opposite sides of the first width. Additionally, the method includes doping a first dopant of a first concentration through the first opening into a first thickness of the waveguide to form a first semiconducting phase thereof. The method includes providing a second mask with a second opening exposing part of the waveguide and doping a second dopant of a second concentration through the second opening into the part of the waveguide to form a second semiconductor phase thereof sharing a boundary with the first semiconducting phase to form a PN junction across the boundary. The boundary is allowed to vary with a margin of tolerance within the first width.
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公开(公告)号：US09742550B1
公开(公告)日：2017-08-22
申请号：US15172595
申请日：2016-06-03
Applicant: INPHI CORPORATION
Inventor： Marcel Louis Lugthart , Jeffrey Zachan , Linghsiao Jerry Wang
CPC classification number: H04L7/0037 , H03M5/12 , H04B1/40 , H04L5/14 , H04L7/0016 , H04L7/0054 , H04L7/0062 , H04L7/0087 , H04L7/02 , H04L7/033 , H04L25/03 , H04L25/03006 , H04L25/14 , H04L27/02 , H04L27/38 , H04L47/70
Abstract: Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.
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Patent Agency Ranking
公开(公告)号：US09722621B2
公开(公告)日：2017-08-01
申请号：US15375029
申请日：2016-12-09
Applicant: INPHI CORPORATION
Inventor： Mohammad Ranjbar , Jorge Pernillo
CPC classification number: H03M1/1028 , H03K5/082 , H03M1/1023 , H03M1/36 , H03M1/38 , H03M1/662 , H03M1/68
Abstract: The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.
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公开(公告)号：US20170207908A1
公开(公告)日：2017-07-20
申请号：US15375059
申请日：2016-12-09
Applicant: INPHI CORPORATION
Inventor： Halil CIRIT , Karthik GOPALAKRISHNAN , Pulkit KHANDELWAL , Ravindran MOHANAVELU
CPC classification number: H04L7/0332 , H03L7/00 , H03L7/0807 , H04L5/0048 , H04L7/033 , H04L25/14 , H04L27/02 , H04Q2213/03
Abstract: The present invention is directed to communication systems. According to embodiments of the present invention, a communication system includes at least two communication lanes and a skew management module. The skew management module generates a control current based on output test patterns of the two communication lanes. The control current is integrated and compared to a reference voltage by a comparator, which generates an analog offset signal. A PLL of one of the communication lanes generates a corrected clock signal that is adjusted using the analog offset signal to remove or adjust the skew between the communication lanes. The corrected clock signal is used for output data. There are other embodiments as well.
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公开(公告)号：US20170207904A1
公开(公告)日：2017-07-20
申请号：US15474593
申请日：2017-03-30
Applicant: INPHI CORPORATION
Inventor： Sheldon James HOOD , Paul Thomas BANENS
CPC classification number: H04L7/0016 , H03K5/133 , H03K5/135 , H03K19/00361 , H03K19/21 , H03K2005/00078 , H03L7/0807 , H04B1/04 , H04L25/49
Abstract: When a data path includes CMOS circuitry, such circuitry may introduce into the data signal. Embodiments are described in which additional data transitions are made to occur, and these additional data transitions may change the characteristics of the data frequency content transferred to the power supply so that such noise may be better filtered. This may have an effect of reducing jitter in the data signal. In one embodiment, a second data signal is generated to be a version of a first data signal with every second bit inverted. Second CMOS circuitry receives the second data signal in parallel to first CMOS circuitry receiving the first data signal. The first CMOS circuitry and the second CMOS circuitry are connected to a same power supply.
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259.发明授权公开(公告)号：US09712253B1
公开(公告)日：2017-07-18
申请号：US14869676
申请日：2015-09-29
Applicant: Inphi Corporation
Inventor： Mario Rafael Hueda , Mauro M. Bruni , Federico Nicolas Paredes , Hugo Santiago Carrer , Diego Ernesto Crivelli , Oscar Ernesto Agazzi , Norman L. Swenson , Seyedmohammadreza Motaghiannezam
CPC classification number: H04B10/6162 , H04B10/616 , H04B10/6165 , H04L7/0075 , H04L7/0079
Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.
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公开(公告)号：US20170194970A1
公开(公告)日：2017-07-06
申请号：US15464750
申请日：2017-03-21
Applicant: INPHI CORPORATION
Inventor： Karthik S. GOPALAKRISHNAN , Guojun REN , Parmanand MISHRA
CPC classification number: H03L7/0812 , H03K5/131 , H03K5/135 , H03K5/14 , H03K2005/00013 , H03K2005/00052 , H03K2005/00286 , H03L3/00 , H03L7/08 , H03L7/0807 , H03L7/0814 , H04L5/0053 , H04L7/002 , H04L7/0331 , H04L25/03273 , H04L27/04
Abstract: The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for regulating a voltage for a high speed serializer/deserializer (SerDes) device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications. In various embodiments, phase-interpolator is implemented in conjunction with a delay-lock loop (DLL) and an SR latch, where one or more outputs of the DLL is used by the SR latch. Additionally, such techniques can be used for a variety of applications such as network and/or computer storage systems, computer servers, hand held computing devices, portable computing devices, computer systems, network appliances and/or switches, routers, and gateways, and the like.
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