中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

90 records (took 0.017 seconds)

    Synchronous dynamic random access memory semiconductor device for controlling output data
    21.
    发明授权
    Synchronous dynamic random access memory semiconductor device for controlling output data 有权
    用于控制输出数据的同步动态随机存取存储器半导体器件

    公开(公告)号：US08325544B2

    公开(公告)日：2012-12-04

    申请号：US12702809

    申请日：2010-02-09

    Applicant: Sang-kyu Kang ,  Ho-cheol Lee ,  Chi-sung Oh

    Inventor： Sang-kyu Kang ,  Ho-cheol Lee ,  Chi-sung Oh

    IPC: G11C7/00

    CPC classification number: G11C7/1072 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    Abstract: Provided is a synchronous dynamic random access memory (DRAM) semiconductor device including multiple output buffers, a strobe control unit and multiple strobe buffers. Each of the output buffers is configured to output one bit of data. The strobe control unit is configured to output multiple strobe control signals in response to an externally input signal. The strobe buffers are connected to the output buffers and the strobe control unit, and each of the strobe buffers is configured to output at least one strobe signal. At least some of the strobe buffers are activated in response to the strobe control signals, and the output buffers are activated in response to the strobe signals output by the activated strobe buffers.

    Abstract translation: 提供了包括多个输出缓冲器，选通控制单元和多个选通缓冲器的同步动态随机存取存储器（DRAM）半导体器件。 每个输出缓冲器都配置为输出一位数据。 选通控制单元被配置为响应于外部输入信号输出多个选通控制信号。 选通缓冲器连接到输出缓冲器和选通控制单元，并且每个选通缓冲器被配置为输出至少一个选通信号。 至少一些选通缓冲器响应于选通控制信号被激活，并且输出缓冲器响应于被激活的选通缓冲器输出的选通信号被激活。

    Method of outputting temperature data in semiconductor device and temperature data output circuit therefor
    22.
    发明授权
    Method of outputting temperature data in semiconductor device and temperature data output circuit therefor 有权
    在半导体器件中输出温度数据的方法及其温度数据输出电路

    公开(公告)号：US08322922B2

    公开(公告)日：2012-12-04

    申请号：US12605032

    申请日：2009-10-23

    Applicant: Yun-Young Lee ,  Kyu-Chan Lee ,  Ho-Cheol Lee

    Inventor： Yun-Young Lee ,  Kyu-Chan Lee ,  Ho-Cheol Lee

    IPC: G01K7/01 ,  G01K7/14

    CPC classification number: G01K7/015 ,  G01K2219/00

    Abstract: A method of outputting temperature data in a semiconductor device and a temperature data output circuit are provided. A pulse signal is generated in response to a booting enable signal activated in response to a power-up signal and the generation is inactivated in response to a mode setting signal during a power-up operation. A comparison signal is generated in response to the pulse signal by comparing a reference voltage independent of temperature with a sense voltage that varies with temperature change. The temperature data is changed in response to the comparison signal. Thus, the temperature data output circuit can rapidly output the exact temperature of the semiconductor device measured during the power-up operation.

    Abstract translation: 提供了一种在半导体器件和温度数据输出电路中输出温度数据的方法。 响应于响应于上电信号而被激活的引导使能信号而产生脉冲信号，并且响应于上电操作期间的模式设置信号而使生成失效。 通过将与温度无关的参考电压与随温度变化而变化的感测电压进行比较，响应于脉冲信号产生比较信号。 响应于比较信号来改变温度数据。 因此，温度数据输出电路可以快速输出在上电操作期间测量的半导体器件的精确温度。

    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME
    23.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME 审中-公开
    具有它的半导体存储器件和存储器系统

    公开(公告)号：US20120188834A1

    公开(公告)日：2012-07-26

    申请号：US13441713

    申请日：2012-04-06

    Applicant: Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

    Inventor： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

    IPC: G11C7/22

    CPC classification number: G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

    Abstract: A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.

    Abstract translation: 公开了一种半导体存储器件。 半导体器件包括存储单元阵列，时钟信号发生器，被配置为从存储器件的外部接收外部时钟信号并输出​​内部时钟信号;以及数据输出单元，被配置为从存储器单元接收内部数据信号 阵列并响应于内部时钟信号输出读取数据信号。 半导体存储器件还包括读取数据选通单元，其被配置为基于内部时钟信号的周期时间，输出具有n倍（n是等于或大于2的整数）的周期时间的读取数据选通信号 内部时钟信号。

    Self-refresh control circuit and semiconductor memory device including the same
    27.
    发明授权
    Self-refresh control circuit and semiconductor memory device including the same 有权
    自刷新控制电路和包括其的半导体存储器件

    公开(公告)号：US07649797B2

    公开(公告)日：2010-01-19

    申请号：US12031110

    申请日：2008-02-14

    Applicant: Soo-Man Hwang ,  Ho-Cheol Lee

    Inventor： Soo-Man Hwang ,  Ho-Cheol Lee

    IPC: G11C7/22

    CPC classification number: G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4087 ,  G11C2211/4065 ,  G11C2211/4068

    Abstract: A refresh control circuit in a semiconductor memory device includes a refresh controller, a voltage generator and a word line enable circuit. The refresh period controller generates a control signal in response to a self-refresh signal, the control signal indicating a nominal initiation of a refresh period. The voltage generator generates an output voltage in response to the control signal. The output voltage is boosted from a low voltage to a high voltage during the refresh period. The word line enable circuit generates a word line enable signal in response to the control signal, wherein the word line enable signal is activated following a delay after the nominal initiation of the refresh period, and the delay allows the voltage generator to fully boost the output voltage.

    Abstract translation: 半导体存储器件中的刷新控制电路包括刷新控制器，电压发生器和字线使能电路。 刷新周期控制器响应于自刷新信号产生控制信号，该控制信号指示刷新周期的标称启动。 电压发生器响应于控制信号产生输出电压。 在刷新期间，输出电压从低电压升压到高电压。 字线使能电路响应于控制信号产生字线使能信号，其中在刷新周期的标称启动之后的延迟之后，字线使能信号被激活，并且延迟允许电压发生器完全提升输出 电压。

    SELF-REFRESH CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    29.
    发明申请
    SELF-REFRESH CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
    自熔控制电路和包括其的半导体存储器件

    公开(公告)号：US20080205183A1

    公开(公告)日：2008-08-28

    申请号：US12031110

    申请日：2008-02-14

    Applicant: Soo-Man HWANG ,  Ho-Cheol LEE

    Inventor： Soo-Man HWANG ,  Ho-Cheol LEE

    IPC: G11C7/00

    CPC classification number: G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4087 ,  G11C2211/4065 ,  G11C2211/4068

    Abstract: A refresh control circuit in a semiconductor memory device includes a refresh controller, a voltage generator and a word line enable circuit. The refresh period controller generates a control signal in response to a self-refresh signal, the control signal indicating a nominal initiation of a refresh period. The voltage generator generates an output voltage in response to the control signal. The output voltage is boosted from a low voltage to a high voltage during the refresh period. The word line enable circuit generates a word line enable signal in response to the control signal, wherein the word line enable signal is activated following a delay after the nominal initiation of the refresh period, and the delay allows the voltage generator to fully boost the output voltage.

    Abstract translation: 半导体存储器件中的刷新控制电路包括刷新控制器，电压发生器和字线使能电路。 刷新周期控制器响应于自刷新信号产生控制信号，该控制信号指示刷新周期的标称启动。 电压发生器响应于控制信号产生输出电压。 在刷新期间，输出电压从低电压升压到高电压。 字线使能电路响应于控制信号产生字线使能信号，其中在刷新周期的标称启动之后的延迟之后，字线使能信号被激活，并且延迟允许电压发生器完全提升输出 电压。

    Multiprocessor system and method thereof
    30.
    发明申请
    Multiprocessor system and method thereof 有权
    多处理器系统及其方法

    公开(公告)号：US20080172516A1

    公开(公告)日：2008-07-17

    申请号：US11819601

    申请日：2007-06-28

    Applicant: Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

    Inventor： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

    IPC: G06F12/02

    CPC classification number: G06F12/02

    Abstract: A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

    Abstract translation: 提供了一种多处理器系统及其方法。 示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组 处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的 通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址， 通过第二个端口，银行地址选择第四个存储器，作为银行地址作为银行地址，选择第三个存储器 银行通过第一个港口。

Patent Agency Ranking