公开(公告)号：US09276112B2

公开(公告)日：2016-03-01

申请号：US13886939

申请日：2013-05-03

Applicant: Mark T. Bohr

Inventor： Mark T. Bohr

IPC: H01L29/737 ,  H01L29/78 ,  H01L29/04 ,  H01L29/66 ,  H01L21/84 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/845 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7378 ,  H01L29/7834 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.

公开(公告)号：US20150332994A1

公开(公告)日：2015-11-19

申请号：US14813014

申请日：2015-07-29

Applicant: Debendra MALLIK ,  Ram S. VISWANATH ,  Sriram SRINIVASAN ,  Mark T. BOHR ,  Andrew W. YEOH ,  Sairam AGRAHARAM

Inventor： Debendra MALLIK ,  Ram S. VISWANATH ,  Sriram SRINIVASAN ,  Mark T. BOHR ,  Andrew W. YEOH ,  Sairam AGRAHARAM

IPC: H01L23/498 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00

Abstract: 3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.

Abstract translation: 描述了具有窗口插入件的3D集成电路封装和形成这种半导体封装的方法。 例如，半导体封装包括衬底。 顶部半导体管芯设置在衬底上方。 具有窗口的插入件设置在基板和顶部半导体管芯之间并与之互连。 底部半导体管芯设置在插入件的窗口中并且互连到顶部半导体管芯。 在另一示例中，半导体封装包括衬底。 顶部半导体管芯设置在衬底上。 插入器设置在衬底和顶部半导体管芯之间并且互连到衬底和顶部半导体管芯。 底部半导体管芯设置在与插入器相同的平面中并且互连到顶部半导体管芯。

公开(公告)号：US09142510B2

公开(公告)日：2015-09-22

申请号：US13994666

申请日：2011-10-28

Applicant: Kevin J. Lee ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Christopher M. Pelto ,  Hiten Kothari ,  Seshu V. Sattiraju ,  Hang-Shing Ma

Inventor： Kevin J. Lee ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Christopher M. Pelto ,  Hiten Kothari ,  Seshu V. Sattiraju ,  Hang-Shing Ma

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/538 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L21/683

CPC classification number: H01L23/5384 ,  H01L21/6835 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5286 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/17 ,  H01L2221/6835 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17106 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/186 ,  H01L2924/381 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.

Abstract translation: 描述了3D互连结构和制造方法，其中使用双镶嵌型工艺流程形成穿硅通孔（TSV）和金属再分布层（RDL）。 氮化硅或碳化硅钝化层可以设置在减薄的器件晶片背面和RDL之间，以在工艺流程期间提供气密屏障和蚀刻停止层。

公开(公告)号：US20130224926A1

公开(公告)日：2013-08-29

申请号：US13857578

申请日：2013-04-05

Applicant: Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chai-Hong Jan ,  Mark T. Bohr

Inventor： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chai-Hong Jan ,  Mark T. Bohr

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

公开(公告)号：US08101485B2

公开(公告)日：2012-01-24

申请号：US11305465

申请日：2005-12-16

Applicant: Mark T. Bohr

Inventor： Mark T. Bohr

IPC: H01L21/336

CPC classification number: H01L21/823814 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11807 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

Abstract: Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.

Abstract translation: 本发明的一些实施例包括与NMOS和PMOS晶体管应变相关的装置和方法。

公开(公告)号：US20110215422A1

公开(公告)日：2011-09-08

申请号：US13107783

申请日：2011-05-13

Applicant: Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

Inventor： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

IPC: H01L21/8238 ,  H01L29/36 ,  H01L29/78

CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract translation: 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

公开(公告)号：US07494858B2

公开(公告)日：2009-02-24

申请号：US11173660

申请日：2005-06-30

Applicant: Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

Inventor： Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

IPC: H01L21/336

CPC classification number: H01L29/045 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

Abstract translation: 实施例是改进的晶体管结构和制造该结构的方法。 特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能 并且在源极和漏极与硅化物之间的界面处降低接触电阻。

公开(公告)号：US06624032B2

公开(公告)日：2003-09-23

申请号：US10102319

申请日：2002-03-20

Applicant: Mohsen Alavi ,  Ebrahim Andideh ,  Scott Thompson ,  Mark T. Bohr

Inventor： Mohsen Alavi ,  Ebrahim Andideh ,  Scott Thompson ,  Mark T. Bohr

IPC: H01L21336

CPC classification number: H01L29/66666 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7841

Abstract: A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.

公开(公告)号：US06566737B2

公开(公告)日：2003-05-20

申请号：US09115418

申请日：1998-07-14

Applicant: Mark T. Bohr

Inventor： Mark T. Bohr

IPC: H01L2358

CPC classification number: H01L24/05 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A novel passivation structure and its method of fabrication. According to the present invention a first dielectric layer is formed upon a conductive layer formed over a substrate. The first dielectric layer and the conductive layer are then patterned into a first dielectric capped interconnect and a dielectric capped bond pad. Next, a second dielectric layer is formed over and between the dielectric capped interconnect and the dielectric capped bond pad. The top portion of the second dielectric layer is removed so as to expose the dielectric capped bond pad and the dielectric capped interconnect. A third dielectric layer is then formed over the exposed dielectric capped bond pad and the exposed dielectric capped interconnect and over the second dielectric.

Abstract translation: 一种新颖的钝化结构及其制造方法。 根据本发明，在形成在基板上的导电层上形成第一介电层。 然后将第一电介质层和导电层图案化成第一介电覆盖的互连和介电覆盖的接合焊盘。 接下来，在电介质封盖互连和介电封闭的接合焊盘之间并且之间形成第二电介质层。 去除第二电介质层的顶部，以便露出介质封盖的接合焊盘和介电封闭的互连。 然后在暴露的电介质封盖接合焊盘和暴露的电介质封盖互连件上并在第二电介质上形成第三电介质层。

公开(公告)号：US06392271B1

公开(公告)日：2002-05-21

申请号：US09342022

申请日：1999-06-28

Applicant: Mohsen Alavi ,  Ebrahim Andideh ,  Scott Thompson ,  Mark T. Bohr

Inventor： Mohsen Alavi ,  Ebrahim Andideh ,  Scott Thompson ,  Mark T. Bohr

IPC: H01L2976

CPC classification number: H01L29/66666 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7841

Abstract: A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer sited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.

Abstract translation: 一种双栅极晶体管器件及其制造方法。 首先，在掺杂衬底上的图案化氧化物层上制备掺杂衬底，其限定沟道。 接下来，沉积硅层以形成沟道，然后栅极氧化层在沟道附近生长。 随后，在栅氧化层旁边形成多个栅电极，在沟道上形成漏极。 在形成漏极之后，设置ILD层。 该ILD层被蚀刻以形成源极区接触，漏极区接触，第一栅电极接触和第二栅电极接触。