公开(公告)号：US07390581B2

公开(公告)日：2008-06-24

申请号：US11431990

申请日：2006-05-11

Applicant: Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

Inventor： Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

IPC: B32B9/00 ,  C30B25/00

CPC classification number: C30B29/403 ,  C30B25/18 ,  C30B29/406 ,  H01L29/045 ,  H01L29/2003 ,  Y10T83/0524 ,  Y10T428/31

Abstract: A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the direction predominantly toward a direction selected from the group consisting of and directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm−2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

Abstract translation: III-V族氮化物，例如GaN，衬底，其包括从<0001>方向切除的（0001）表面主要朝向选自<10-10>和<11-20>方向的方向切割 在约0.2至约10度的范围内的角度，其中表面具有通过50×50μm2μmAFM扫描测量的RMS粗糙度小于1nm，位错密度小于 3E6厘米-2。 可以通过在对应的邻位异质外延基底（例如切断蓝宝石）上的基底主体的切削研磨或生长来对对应的原子块或晶片坯料进行切割切片来形成基底。 在制造III-V族氮化物微电子和光电子器件时，该衬底有效地用于同质外延沉积。

公开(公告)号：US07170095B2

公开(公告)日：2007-01-30

申请号：US10618024

申请日：2003-07-11

Applicant: Robert P. Vaudo ,  Xueping Xu ,  George R. Brandes

Inventor： Robert P. Vaudo ,  Xueping Xu ,  George R. Brandes

IPC: H01L29/15 ,  H01L21/20 ,  C23C16/24

CPC classification number: H01L29/207 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02581 ,  H01L21/0262 ,  H01L29/2003

Abstract: Large-area, single crystal semi-insulating gallium nitride that is usefully employed to form substrates for fabricating GaN devices for electronic and/or optoelectronic applications. The large-area, semi-insulating gallium nitride is readily formed by doping the growing gallium nitride material during growth thereof with a deep acceptor dopant species, e.g., Mn, Fe, Co, Ni, Cu, etc., to compensate donor species in the gallium nitride, and impart semi-insulating character to the gallium nitride.

Abstract translation: 大面积的单晶半绝缘氮化镓，其有效地用于形成用于制造用于电子和/或光电应用的GaN器件的衬底。 大面积半绝缘氮化镓容易通过在其生长期间掺杂生长的氮化镓材料与深受主掺杂物质（例如Mn，Fe，Co，Ni，Cu等）来形成，以补偿在 氮化镓，并赋予氮化镓半绝缘特性。

公开(公告)号：US20060029832A1

公开(公告)日：2006-02-09

申请号：US11213535

申请日：2005-08-26

Applicant: Xueping Xu ,  Robert Vaudo

Inventor： Xueping Xu ,  Robert Vaudo

IPC: B32B3/02 ,  B32B9/00 ,  B32B19/00

CPC classification number: C30B33/00 ,  C09G1/02 ,  C09K3/1409 ,  C09K3/1463 ,  C30B25/02 ,  C30B29/403 ,  H01L21/02005 ,  H01L21/02019 ,  H01L21/02024 ,  H01L21/30617 ,  H01L33/0075 ,  Y10T428/21

Abstract: AlxGayInzN, wherein 0≦x≦1, 0≦y≦1, 0≦z≦1, and x+y+z=1, characterized by a root mean square surface roughness of less than 1 nm in a 10×10 μm2 area. The AlxGayInzN may be in the form of a wafer, which is chemically mechanically polished (CMP) using a CMP slurry comprising abrasive particles, such as silica or alumina, and an acid or a base. High quality AlxGayInzN wafers can be fabricated by steps including lapping, mechanical polishing, and reducing internal stress of said wafer by thermal annealing or chemical etching for further enhancement of its surface quality. CMP processing may be usefully employed to highlight crystal defects of an AlxGayInzN wafer.

Abstract translation: 其中0 <= x <=1,0,0≤y≤1,0

公开(公告)号：US5973444A

公开(公告)日：1999-10-26

申请号：US191269

申请日：1998-11-12

Applicant: Xueping Xu ,  Charles P. Beetz ,  George R. Brandes ,  Robert W. Boerstler ,  John W. Steinbeck

Inventor： Xueping Xu ,  Charles P. Beetz ,  George R. Brandes ,  Robert W. Boerstler ,  John W. Steinbeck

IPC: H01J1/304 ,  H01J1/30

CPC classification number: H01J1/304 ,  B82Y10/00 ,  H01J2201/30469 ,  H01J2201/319 ,  Y10S977/939

Abstract: Electron field emission devices (cold cathodes), vacuum microelectronic devices and field emission displays which incorporate cold cathodes and methods of making and using same. More specifically, cold cathode devices comprising electron emitting structures grown directly onto a substrate material. The invention also relates to patterned precursor substrates for use in fabricating field emission devices and methods of making same and also to catalytically growing other electronic structures, such as films, cones, cylinders, pyramids or the like, directly onto substrates.

公开(公告)号：US08728236B2

公开(公告)日：2014-05-20

申请号：US13008008

申请日：2011-01-17

Applicant: Xueping Xu ,  Robert P. Vaudo

Inventor： Xueping Xu ,  Robert P. Vaudo

IPC: C30B25/02

CPC classification number: C30B29/406 ,  C30B25/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/0254 ,  H01L31/184 ,  H01L33/0075 ,  Y10T428/21 ,  Y10T428/265

Abstract: Large area single crystal III-V nitride material having an area of at least 2 cm2, having a uniformly low dislocation density not exceeding 3×106 dislocations per cm2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

Abstract translation: 具有至少2cm 2面积的大面积单晶III-V族氮化物材料，具有均匀低位错密度，每平方厘米生长表面积不超过3×106位错，并且包括具有升高的杂质浓度的多个不同区域，其中 每个不同的区域具有大于50微米的至少一个尺寸。 这样的材料可以通过以下工艺在基底上形成，该方法包括：（i）在凹陷生长条件下在衬底上生长III-V族氮化物材料的第一相，例如在III的生长表面的至少50％上形成凹坑 -V氮化物材料，其中生长表面上的凹坑密度为生长表面的至少102个凹坑/ cm 2，和（ii）在凹坑填充条件下生长III-V族氮化物材料的第二阶段。

公开(公告)号：US08043731B2

公开(公告)日：2011-10-25

申请号：US12713514

申请日：2010-02-26

Applicant: Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

Inventor： Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

IPC: B32B18/00 ,  B32B11/08

CPC classification number: C30B29/403 ,  C30B25/18 ,  C30B29/406 ,  H01L29/045 ,  H01L29/2003 ,  Y10T83/0524 ,  Y10T428/31

Abstract: A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the direction predominantly toward a direction selected from the group consisting of and directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3 E6 cm−2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. Both upper and lower surfaces may be offcut. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

Abstract translation: III-V族氮化物，例如GaN，衬底，其包括从<0001>方向切除的（0001）表面主要朝向选自<10-10>和<11-20>方向的方向切割 在约0.2至约10度的范围内的角度，其中表面具有通过50×50μm2 AFM扫描测量的RMS粗糙度小于1nm，位错密度小于3E6cm-2。 可以通过在对应的邻位异质外延基底（例如切断蓝宝石）上的基底主体的切削研磨或生长来对对应的原子块或晶片坯料进行切割切片来形成基底。 上表面和下表面都可以被切断。 在制造III-V族氮化物微电子和光电子器件时，该衬底有效地用于同质外延沉积。

公开(公告)号：US20110198590A1

公开(公告)日：2011-08-18

申请号：US13015303

申请日：2011-01-27

Applicant: Edward A. Preble ,  Lianghong Liu ,  Andrew D. Hanser ,  N. Mark Williams ,  Xueping Xu

Inventor： Edward A. Preble ,  Lianghong Liu ,  Andrew D. Hanser ,  N. Mark Williams ,  Xueping Xu

IPC: H01L21/20 ,  H01L29/04

CPC classification number: H01L21/02694 ,  C30B25/02 ,  C30B25/18 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/02581 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02631 ,  H01L29/04 ,  H01L29/0688 ,  H01L29/2003 ,  H01L33/007 ,  H01L33/30 ,  H01L33/32

Abstract: In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

Abstract translation: 在制造GaN制品的方法中，在单晶衬底上沉积外延氮化物层。 通过HVPE在基本上3D生长模式下在外延氮化物层上生长3D成核GaN层。 在将成长模式从基本上3D生长模式改变为基本上2D生长模式的条件下，通过HVPE在3D成核层上生长GaN过渡层。 在基本上2D生长模式下，通过HVPE在过渡层上生长体GaN层。 在体GaN层上生长多晶GaN层以形成GaN /衬底双层。 GaN /衬底双层可以从生长温度冷却到环境温度，其中GaN材料横向裂开并与衬底分离，形成独立制品。

公开(公告)号：US07972711B2

公开(公告)日：2011-07-05

申请号：US12026552

申请日：2008-02-05

Applicant: Xueping Xu ,  Robert P. Vaudo

Inventor： Xueping Xu ,  Robert P. Vaudo

IPC: B32B9/00

CPC classification number: C30B29/406 ,  C30B25/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/0254 ,  H01L31/184 ,  H01L33/0075 ,  Y10T428/21 ,  Y10T428/265

Abstract: Large area single crystal III-V nitride material having an area of at least 2 cm2, having a uniformly low dislocation density not exceeding 3×106 dislocations per cm2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

Abstract translation: 具有至少2cm 2面积的大面积单晶III-V族氮化物材料，具有均匀低位错密度，每平方厘米生长表面积不超过3×106位错，并且包括具有升高的杂质浓度的多个不同区域，其中 每个不同的区域具有大于50微米的至少一个尺寸。 这样的材料可以通过以下工艺在基底上形成，该方法包括：（i）在凹陷生长条件下在衬底上生长III-V族氮化物材料的第一相，例如在III的生长表面的至少50％上形成凹坑 -V氮化物材料，其中生长表面上的凹坑密度为生长表面的至少102个凹坑/ cm 2，和（ii）在凹坑填充条件下生长III-V族氮化物材料的第二阶段。

公开(公告)号：US20110042682A1

公开(公告)日：2011-02-24

申请号：US12855087

申请日：2010-08-12

Applicant: Edward A. Preble ,  Denis Tsvetkov ,  Andrew D. Hanser ,  N. Mark Williams ,  Xueping Xu

Inventor： Edward A. Preble ,  Denis Tsvetkov ,  Andrew D. Hanser ,  N. Mark Williams ,  Xueping Xu

IPC: H01L29/12 ,  H01L21/20

CPC classification number: H01L21/02694 ,  C30B25/02 ,  C30B25/18 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/02581 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02631 ,  H01L29/04 ,  H01L29/0688 ,  H01L29/2003 ,  H01L33/007 ,  H01L33/30 ,  H01L33/32

Abstract: In a method for making an inclusion-free uniformly semi-insulating GaN crystal, an epitaxial nitride layer is deposited on a substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode, wherein a surface of the nucleation layer is substantially covered with pits and the aspect ratio of the pits is essentially the same. A GaN transitional layer is grown on the nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. After growing the transitional layer, a surface of the transitional layer is substantially pit-free. A bulk GaN layer is grown on the transitional layer by HVPE. After growing the bulk layer, a surface of the bulk layer is smooth and substantially pit-free. The GaN is doped with a transition metal during at least one of the foregoing GaN growth steps.

Abstract translation: 在制造无夹杂物的均匀半绝缘GaN晶体的方法中，在衬底上沉积外延氮化物层。 3D成核GaN层通过HVPE在基本上3D生长模式下在外延氮化物层上生长，其中成核层的表面基本上被凹坑覆盖，并且凹坑的纵横比基本相同。 在将生长模式从基本上3D生长模式改变为基本上2D生长模式的条件下，通过HVPE在成核层上生长GaN过渡层。 在生长过渡层之后，过渡层的表面基本上是无凹坑的。 通过HVPE在过渡层上生长体GaN层。 在生长本体层之后，本体层的表面是光滑的并且基本上无凹坑。 在至少一个上述GaN生长步骤期间，GaN掺杂有过渡金属。

公开(公告)号：US07884447B2

公开(公告)日：2011-02-08

申请号：US11994406

申请日：2006-06-27

Applicant: George R. Brandes ,  Robert P. Vaudo ,  Xueping Xu

Inventor： George R. Brandes ,  Robert P. Vaudo ,  Xueping Xu

IPC: H01L29/04

CPC classification number: H01S5/32341 ,  Y10S438/973

Abstract: A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate (201). In an illustrative implementation, a laser diode is oriented on a GaN substrate (201) wherein the GaN substrate includes a GaN (0001) surface off-cut from the direction predominantly towards either the or the family of directions. For a off-cut substrate, a laser diode cavity (207) may be oriented along the direction parallel to lattice surface steps (202) of the substrate (201) in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For off-cut substrate, the laser diode cavity may be oriented along the direction orthogonal to lattice surface steps (207) of the substrate (201) in order to provide a cleave laser facet that is aligned with the surface lattice steps.

Abstract translation: 一种微电子组件，其中半导体器件结构定向地定位在离轴衬底（201）上。 在说明性实施方案中，激光二极管定向在GaN衬底（201）上，其中GaN衬底包括从主要朝向<1120>或<1100>族的<0001>方向偏离的GaN（0001）表面 的方向。 对于<1120>截割衬底，激光二极管腔（207）可以沿着平行于衬底（201）的晶格表面台阶（202）的<1100>方向定向，以便具有切割的激光小面 与表面晶格步进正交。 对于<1100>截割衬底，激光二极管空腔可以沿着与衬底（201）的晶格表面台阶（207）正交的<1100>方向定向，以便提供与表面对准的切割激光小面 格子步。