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    Methods for thinning semiconductor substrates that employ support structures formed on the substrates
    21.
    发明授权
    Methods for thinning semiconductor substrates that employ support structures formed on the substrates 有权
    减薄采用在基板上形成的支撑结构的半导体衬底的方法

    公开(公告)号：US07713841B2

    公开(公告)日：2010-05-11

    申请号：US10666742

    申请日：2003-09-19

    申请人： Alan G. Wood ,  Warren M. Farnworth ,  David R. Hembree ,  Sidney B. Rigg ,  William M. Hiatt ,  Peter Benson ,  Kyle K. Kirby ,  Salman Akram

    发明人： Alan G. Wood ,  Warren M. Farnworth ,  David R. Hembree ,  Sidney B. Rigg ,  William M. Hiatt ,  Peter Benson ,  Kyle K. Kirby ,  Salman Akram

    IPC分类号： H01L21/46

    CPC分类号： G03F7/0037 ,  B33Y30/00 ,  B33Y70/00 ,  B33Y80/00 ,  G03F7/0047

    摘要： A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion which extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member which substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface. Assemblies that include the support structure and a semiconductor substrate are also within the scope of the present invention, as are methods for forming the support structures and thinning and post-thinning processes that include use of the support structures.

    摘要翻译： 在半导体衬底的薄化或后研磨以及后稀化处理期间与半导体衬底一起使用的支撑结构包括基本上沿半导体衬底的外周延伸并且围绕半导体衬底的外周延伸的部分，以使薄化半导体 基板具有刚性。 支撑结构可以被配置为环或作为基本上覆盖半导体衬底的有源表面并且在由有源表面承载的每个半导体器件上形成保护结构的构件。 包括支撑结构和半导体衬底的组件也在本发明的范围内，形成支撑结构的方法和包括使用支撑结构的减薄和后变薄工艺也是如此。

    Method for testing semiconductor components
    26.
    发明授权
    Method for testing semiconductor components 有权
    半导体元件测试方法

    公开(公告)号：US06208157B1

    公开(公告)日：2001-03-27

    申请号：US09298769

    申请日：1999-04-23

    申请人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

    发明人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

    IPC分类号： G01R3102

    CPC分类号： G01R1/0466 ,  G01R1/0433 ,  G01R1/0483

    摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.

    摘要翻译： 提供了一种用于测试半导体部件的系统和方法。 该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装在插座上用于容纳组件的载体。 载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。 此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。 插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。 在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。 然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

    Method, apparatus and system for testing bumped semiconductor components
    27.
    发明授权
    Method, apparatus and system for testing bumped semiconductor components 有权
    用于测试碰撞半导体元件的方法，装置和系统

    公开(公告)号：US6091252A

    公开(公告)日：2000-07-18

    申请号：US312381

    申请日：1999-05-14

    申请人： Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  David R. Hembree

    发明人： Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  David R. Hembree

    IPC分类号： G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R31/28 ,  G01R1/06 ,  G01R31/26

    CPC分类号： G01R1/0466

    摘要： A method, apparatus and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The apparatus includes an interconnect having patterns of contact members adapted to electrically contact the contact bumps. Each contact member includes an array of one or more electrically conductive projections in electrical communication with an associated conductor. The projections form contact members for retaining individual contact bumps on the semiconductor components. The projections can be pillars having angled faces covered with a conductive layer. Alternately the projections can be a material deposited on the substrate, or can be microbumps formed on multi layered tape bonded to the substrate. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.

    摘要翻译： 提供了一种用于与具有接触凸块的半导体部件建立临时电连通的方法，装置和系统。 该装置包括具有适于电接触接触凸点的接触构件图案的互连。 每个接触构件包括与相关导体电连通的一个或多个导电突起的阵列。 突起形成接触构件，用于保持半导体部件上的各个接触凸块。 突起可以是具有覆盖有导电层的成角度表面的柱。 替代地，突起可以是沉积在基底上的材料，或者可以是在结合到基底的多层带上形成的微胶囊。 互连可以用于晶片级测试系统中，用于测试包含在晶片上的骰子，或者在用于测试裸露骰子或凸起的芯片级封装的芯片级测试系统中。

    Probe card for semiconductor wafers and method and system for testing wafers
    28.
    发明授权
    Probe card for semiconductor wafers and method and system for testing wafers 失效
    半导体晶圆探针卡及晶圆测试方法及系统

    公开(公告)号：US6060891A

    公开(公告)日：2000-05-09

    申请号：US797719

    申请日：1997-02-11

    申请人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

    发明人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

    IPC分类号： G01R1/073 ,  G01R31/28

    CPC分类号： G01R1/073 ,  G01R31/2886

    摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.

    摘要翻译： 提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。 探针卡被配置用于与测试电路电连通的常规测试装置，例如晶片探测器处理器。 探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。 探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。 互连衬底可以由具有穿透突起的凸起接触构件的硅形成。 或者，接触构件可以形成为用于测试凸起的晶片的凹陷。 膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。 探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

    Interconnect for making temporary electrical connections with bumped semiconductor components
    29.
    发明授权
    Interconnect for making temporary electrical connections with bumped semiconductor components 失效
    互连用于与凸起的半导体元件进行临时电连接

    公开(公告)号：US5931685A

    公开(公告)日：1999-08-03

    申请号：US867551

    申请日：1997-06-02

    申请人： David R. Hembree ,  John O. Jacobson ,  James M. Wark ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood

    发明人： David R. Hembree ,  John O. Jacobson ,  James M. Wark ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood

    IPC分类号： G01R1/04 ,  H01L21/00 ,  H01R12/04 ,  H05K3/32 ,  H01R9/09

    CPC分类号： H01L21/67144 ,  G01R1/0408 ,  H05K3/326 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81385

    摘要： An interconnect and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The interconnect includes a substrate with patterns of contact members adapted to electrically contact the contact bumps. The substrate can be formed of a material such as ceramic, silicon, FR-4, or photo-chemically machineable glass. The contact members can be formed as recesses covered with conductive layers in electrical communication with conductors and terminal contacts on the substrate. Alternately, the contact members can be formed as projections adapted to penetrate the contact bumps, as microbumps with a rough textured surface, or as a deposited layer formed with recesses. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.

    摘要翻译： 提供了一种用于与具有接触凸块的半导体部件建立临时电连通的互连和系统。 互连包括具有适于电接触接触凸块的接触部件图案的基板。 衬底可由诸如陶瓷，硅，FR-4或光刻化学可加工玻璃的材料形成。 接触构件可以形成为覆盖有与衬底上的导体和端子触点电连通的导电层的凹陷。 或者，接触构件可以形成为适于穿透接触凸块的突起，作为具有粗糙纹理表面的微胶囊，或者形成为具有凹陷的沉积层。 互连可以用于晶片级测试系统中，用于测试包含在晶片上的骰子，或者用于测试裸露的骰子或凸起的芯片级封装的芯片级测试系统。