摘要:
A method of operating a phase-change memory array. The method may comprise causing a first current to flow through a phase-change memory element in a first direction and causing a second current to flow through the memory element in a second direction.
摘要:
The invention relates to a method for producing a TFA image sensor in which a multi-layer arrangement comprising a photo diode matrix is arranged on an ASIC switching circuit provided with electronic circuits for operating the TFA image sensor, such as pixel electronics, peripheral electronics and system electronics, for the pixel-wise conversion of electromagnetic radiation into an intensity-dependent photocurrent, the pixels being connected to contacts of the underlying pixel electronics of the ASIC switching circuit. The method enables conventionally produced ASIC switching circuits to be used without impairing the topography of the photoactive sensor surface. The CMOS passivation layer in the photoactive region and then the upper CMOS metallization are removed and replaced by a metallic layer which is structured in the pixel raster, for the formation of back electrodes. The photo diode matrix is then applied and structured, said photo diode matrix being embodied as a pixel matrix, on which a passivating protective layer and/or a color filter layer having a passivating action can be applied.
摘要:
The present invention relates to a new method of preparing gaboxadol (THIP), which is useful for treating sleep disorders. In particular a method of preparing THIP comprising reacting a compound of formula (8b) or a salt thereof with an acid, typically a mineral acid, to obtain THIP as an acid addition salt. The present invention also relates to several intermediates.
摘要:
The source area (3) is highly doped, like the channel area, for the same conductance type. The drain area (4) is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as the well connection or substrate connection.
摘要:
A semiconductor memory having memory cells, each memory cell includes a selection transistor and a trench capacitor. The selection transistor is formed in the form of a vertical transistor. In such a case, two word lines are separated only by a connecting channel that enables an electrically conductive connection between a trench filling of the trench capacitor and a bit line.
摘要:
Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.
摘要:
An integrated memory is described which has a memory cell array with column lines and row lines. A row access controller serves for activating one of the row lines and for controlling a deactivation operation. An input of a control unit is connected to a signal terminal for a signal that, in the event of a read access to one of the memory cells, defines the beginning of data outputting to a point outside the memory cell array. The data output is synchronized with a clock signal. In this case, the signal is adjustable depending on an operating frequency of the memory. An output signal of the control unit serves for triggering the deactivation operation of one of the row lines after a write access. Therefore, in the event of a write access, a comparatively high data throughput is possible even at different operating frequencies of the integrated memory.
摘要:
According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate.
摘要:
A data retention monitor for a memory cell including a voltage source and a voltage comparator. The voltage source is adapted to provide a selectable voltage to the memory cell. The selectable voltage includes a read voltage and a test voltage, with the test voltage being greater than the read voltage. The voltage comparator is adapted to compare a voltage of the memory cell with a reference voltage after the provision of the selectable voltage to the memory cell. The memory cell retains data when the memory cell voltage generated at least in part by the test voltage is substantially equal to the reference voltage.
摘要:
The invention relates a substrate for a package for an electronic circuit and methods for packaging an electronic circuit with a substrate. The substrate comprises at least one conduction region and an activation region arranged within the substrate. The activation region is generally in contact with the conduction region and is configured to change its electrical resistance when activation occurs.