公开(公告)号：US20080233839A1

公开(公告)日：2008-09-25

申请号：US11727119

申请日：2007-03-23

申请人： Hsin-Hsien Lu ,  Liang-Guang Chen ,  Tien-I Bao ,  Shau-Lin Shue

发明人： Hsin-Hsien Lu ,  Liang-Guang Chen ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： C25F3/30

CPC分类号： B24B37/22 ,  B24B37/042 ,  B24B37/24

摘要： Embodiments of a polisher for chemical mechanical planarization. The polisher includes a polishing pad structure containing a first reactant therein, and a second reactant in a polishing environment over the polishing pad structure. The first reactant and the second reactant react endothermically upon contact when polishing a wafer surface between the polishing pad structure and the polishing environment.

摘要翻译： 用于化学机械平面化的抛光机的实施例。 抛光机包括在其中包含第一反应物的抛光垫结构和在抛光环境中的抛光垫结构上的第二反应物。 当抛光抛光垫结构和抛光环境之间的晶片表面时，第一反应物和第二反应物在接触时发生吸热反应。

公开(公告)号：US07405151B2

公开(公告)日：2008-07-29

申请号：US11420900

申请日：2006-05-30

申请人： Gin Jei Wang ,  Chao-Hsien Peng ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Gin Jei Wang ,  Chao-Hsien Peng ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/28562 ,  H01L21/31625 ,  H01L23/482 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device is described. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an atomic layer deposited (ALD) TaN barrier is conformably formed in the opening, at a thickness less than 20 Å. A copper layer is formed over the atomic layer deposited (ALD) TaN barrier to fill the opening.

摘要翻译： 对半导体装置的形成方法进行说明。 在第一电介质层中形成开口，暴露晶体管的有源区，并且在开口中以厚度小于等于一致地形成原子层沉积（ALD）TaN势垒。 在原子层沉积（ALD）TaN势垒上形成铜层以填充开口。

公开(公告)号：US20080121929A1

公开(公告)日：2008-05-29

申请号：US11523683

申请日：2006-09-19

申请人： Jerry Lai ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Jerry Lai ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L29/78

CPC分类号： H01L29/66636 ,  H01L21/26506 ,  H01L21/2652 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/7848 ,  Y10S438/933

摘要： A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer has a first atomic percentage of the element to the element and silicon, a second silicon-containing layer comprising the element over the first silicon-containing layer, and a silicide layer on the second silicon-containing layer. The element in the second silicon-containing layer has a second atomic percentage of the element to the element and silicon, wherein the second atomic percentage is substantially lower than the first atomic percentage.

公开(公告)号：US07312531B2

公开(公告)日：2007-12-25

申请号：US11261200

申请日：2005-10-28

申请人： Hui-Lin Chang ,  Yung-Cheng Lu ,  Chung-Chi Ko ,  Pi-Tsung Chen ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Hung-Wen Su ,  Ming-Hsing Tsai

发明人： Hui-Lin Chang ,  Yung-Cheng Lu ,  Chung-Chi Ko ,  Pi-Tsung Chen ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Hung-Wen Su ,  Ming-Hsing Tsai

IPC分类号： H01L29/40 ,  H01L21/44

CPC分类号： H01L23/53276 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5226 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods for fabricating the same. The devices include a substrate, a catalyst layer, a second dielectric layer, and carbon nanotubes (CNTs). The substrate comprises an overlying first dielectric layer with an electrode embedded therein. The catalyst layer overlies the electrode and the first dielectric layer and substantially comprises Co and M1, wherein M1 is selected from a group consisting of W, P, B, Bi, Ni, and a combination thereof. The second dielectric layer overlies the catalyst layer and comprises an opening exposing parts of the catalyst layer. The carbon nanotubes (CNTs) are disposed on the exposed catalyst layer and electrically connect the electrode.

公开(公告)号：US20070284678A1

公开(公告)日：2007-12-13

申请号：US11838376

申请日：2007-08-14

申请人： Chen-Tung Lin ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Mei-Yun Wang ,  Chiang-Ming Chuang ,  Shau-Lin Shue

发明人： Chen-Tung Lin ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Mei-Yun Wang ,  Chiang-Ming Chuang ,  Shau-Lin Shue

IPC分类号： H01L21/3205 ,  H01L29/45

CPC分类号： H01L29/66545 ,  H01L21/28061 ,  H01L21/28097 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76889 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening by a metal deposition process employing a target which includes metal and silicon. The metal-silicide layer may then be annealed.

摘要翻译： 一种制造微电子器件的方法，包括形成围绕位于衬底上的虚拟特征的介电层，去除虚拟特征以在电介质层中形成开口，以及通过金属沉积工艺形成符合开口的金属硅化物层 使用包括金属和硅的靶。 然后可以将金属硅化物层退火。

公开(公告)号：US07282450B2

公开(公告)日：2007-10-16

申请号：US10733722

申请日：2003-12-11

申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

摘要翻译： 描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。 具体应用是用铜填充沟槽以形成镶嵌线。 首先，通过PVD将种子层沉积在孔或沟槽中。 然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。 描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

公开(公告)号：US20070221993A1

公开(公告)日：2007-09-27

申请号：US11389309

申请日：2006-03-27

申请人： Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Wang ,  Cp Lo ,  Chih-W Chang

发明人： Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Wang ,  Cp Lo ,  Chih-W Chang

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L29/665 ,  H01L21/76243 ,  H01L29/785

摘要： A semiconductor device and method of manufacturing are provided that include forming an alloy layer having the formula MbX over a silicon-containing substrate, where Mb is a metal and X is an alloying additive, the alloy layer being annealed to form a metal alloy silicide layer on the gate region and in active regions of the semiconductor device.

摘要翻译： 提供一种半导体器件和制造方法，包括在含硅衬底上形成具有式MbX的合金层，其中Mb是金属，X是合金添加剂，合金层被退火以形成金属合金硅化物层 在栅极区域和半导体器件的有源区中。

公开(公告)号：US20070181434A1

公开(公告)日：2007-08-09

申请号：US11783245

申请日：2007-04-06

申请人： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

发明人： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

IPC分类号： C25D5/34 ,  H01L21/44 ,  C25D3/38

CPC分类号： H01L21/2885 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle θ less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.

摘要翻译： 电化学沉积（ECD）的方法在衬底上提供阻挡层和种子层。 在将金属层电化学沉积在具有物理或化学表面处理工艺的电化学镀覆电池中之前，对基板的表面进行预处理。 电化学镀覆电池被盖覆盖以防止电解质溶液的蒸发。 电化学电镀单元包括具有提升密封件的衬底保持器组件，例如在提升密封件和衬底之间的接触角θ小于90°。 衬底保持器组件包括在衬底的后侧的衬底卡盘。

公开(公告)号：US07247915B2

公开(公告)日：2007-07-24

申请号：US11375778

申请日：2006-03-15

申请人： Chih-Wei Chang ,  Mei-Yun Wang ,  Shau-Lin Shue ,  Mong-Song Liang

发明人： Chih-Wei Chang ,  Mei-Yun Wang ,  Shau-Lin Shue ,  Mong-Song Liang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L21/28518 ,  H01L29/4941 ,  H01L29/665 ,  H01L29/7833

摘要： A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to transform the bi-layer to a bi-silicide film having a cobalt-rich silicide portion and a nickel-rich silicide portion.

摘要翻译： 一种用于集成电路和半导体器件制造的硅化物方法，其中在镍层上形成在衬底的至少一个硅区域上形成镍层并且形成钴层。 然后退火钴/镍双层以将双层转变为具有富钴硅化物部分和富镍硅化物部分的双硅化物膜。

公开(公告)号：US20070152306A1

公开(公告)日：2007-07-05

申请号：US11324334

申请日：2006-01-04

申请人： Chien-Hsueh Shih ,  Shau-Lin Shue ,  Mong-Song Liang ,  Chao-Hsien Peng

发明人： Chien-Hsueh Shih ,  Shau-Lin Shue ,  Mong-Song Liang ,  Chao-Hsien Peng

IPC分类号： H01L23/58 ,  H01L21/4763

CPC分类号： H01L21/2885 ,  C23C18/1889 ,  C23C18/1893 ,  C25D5/54 ,  C25D13/04 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76877

摘要： A semiconductor device and fabrication method thereof. The semiconductor device comprises a substrate, an electroactive organic layer with conformal step coverage and uniform thickness, and a metal layer. The substrate is a conductive substrate or a nonconductive substrate with a conductive layer formed thereon. The electroactive organic layer and the metal layer are formed sequentially on the conductive substrate or the conductive layer, wherein the electroactive organic layer comprises metal atoms and serves as a seed layer, resulting in the metal layer formed in-situ.

摘要翻译： 半导体器件及其制造方法。 半导体器件包括基底，具有适形阶梯覆盖和均匀厚度的电活性有机层和金属层。 衬底是其上形成有导电层的导电衬底或非导电衬底。 所述电活性有机层和所述金属层依次形成在所述导电性基板或所述导电层上，其中所述电活性有机层包含金属原子并且用作种子层，导致所述金属层原位形成。