公开(公告)号：US20160183376A1

公开(公告)日：2016-06-23

申请号：US14580269

申请日：2014-12-23

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Risto Ilkka Tuominen

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/00 ,  H05K1/09 ,  H05K1/11

CPC classification number: H01L23/49827 ,  H01L22/12 ,  H01L22/14 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/19105 ,  H01L2924/37001

Abstract: An electronic package is provided. The electronic package includes a substrate and a plurality of vias defined by a corresponding plurality of pre-defined via patterns. The electronic package further a metal built-up layer disposed on portions of the substrate to provide a plurality of pre-defined via locations and the plurality of pre-defined via patterns of the plurality of vias. Also, the electronic package includes a first conductive layer disposed on at least a portion of the metal built-up layer. Moreover, the electronic package includes a second conductive layer disposed on the first conductive layer, where the plurality of vias is disposed at least in part in the metal built-up layer, the first conductive layer, and the second conductive layer.

Abstract translation: 提供电子包装。 电子封装包括基板和由相应的多个预定义的通孔图案限定的多个通孔。 电子封装还包括设置在基板的部分上的金属组合层，以提供多个预定义的通孔位置和多个通孔中的多个预定义的通孔图案。 此外，电子封装包括设置在金属叠层的至少一部分上的第一导电层。 此外，电子封装包括设置在第一导电层上的第二导电层，其中多个通孔至少部分地设置在金属组合层，第一导电层和第二导电层中。

公开(公告)号：US09209151B2

公开(公告)日：2015-12-08

申请号：US14037728

申请日：2013-09-26

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/538 ,  H05K1/18 ,  H01L23/34 ,  H05K3/46 ,  H05K1/02 ,  H05K3/30

CPC classification number: H01L23/5389 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/433 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/25 ,  H01L24/26 ,  H01L24/32 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/2518 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0266 ,  H05K1/185 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

Abstract translation: 封装结构包括介电层，至少一个连接到电介质层的半导体器件，一个或多个施加到电介质层的电介质片和半导体器件，以将半导体器件嵌入其中，并且多个 形成在形成在电介质层和一个或多个电介质层中的至少一个中的半导体器件上的通孔。 封装结构还包括形成在通孔中的金属互连和在封装结构的一个或多个向外表面上以形成与半导体器件的电互连的金属互连。 电介质层由在层压过程中不流动的材料组成，并且所述一个或多个电介质片中的每一个由可固化材料构成，所述可固化材料构造成在层压过程中固化时熔化和流动，以便填充任何空气 半导体器件周围的间隙。

公开(公告)号：US20150348952A1

公开(公告)日：2015-12-03

申请号：US14287237

申请日：2014-05-27

Applicant: General Electric Company

Inventor： Gamal Refai-Ahmed ,  David Mulford Shaddock ,  Arun Virupaksha Gowda ,  John Anthony Vogel ,  Christian Giovanniello

IPC: H01L25/16 ,  H01L33/62 ,  H01L23/538 ,  H01L33/54 ,  H01S5/022 ,  H01S5/024 ,  H01L25/00 ,  H01L33/64

CPC classification number: H01L23/5386 ,  H01L23/49811 ,  H01L33/62 ,  H01L2924/0002 ,  H01S5/02256 ,  H05K3/32 ,  H05K2201/0311 ,  H05K2201/10674 ,  H01L2924/00

Abstract: An electronic packaging assembly having a semiconductor integrated circuit and a plurality of interconnect components is provided. The plurality of interconnect components is operatively coupled to the semiconductor integrated circuit. Further, one or more interconnect components include one or more support elements having a first surface and a second surface, and one or more spring elements having a first end and a second end, and wherein first ends of the one or more spring elements are coupled to the first surface or the second surface of a respective support element.

Abstract translation: 提供一种具有半导体集成电路和多个互连部件的电子封装组件。 多个互连部件可操作地耦合到半导体集成电路。 此外，一个或多个互连部件包括具有第一表面和第二表面的一个或多个支撑元件，以及具有第一端和第二端的一个或多个弹簧元件，并且其中一个或多个弹簧元件的第一端连接 到相应的支撑元件的第一表面或第二表面。

公开(公告)号：US20150108513A1

公开(公告)日：2015-04-23

申请号：US14579569

申请日：2014-12-22

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Donald Paul Cunningham ,  Shakti Singh Chauhan

IPC: H01L33/62 ,  H01L33/00 ,  H01L33/60 ,  H01L27/15 ,  H01L33/64

CPC classification number: H05K1/189 ,  H01L25/0753 ,  H01L27/15 ,  H01L33/005 ,  H01L33/60 ,  H01L33/62 ,  H01L33/64 ,  H01L33/642 ,  H01L33/647 ,  H01L2224/24 ,  H01L2933/0066 ,  H01L2933/0075 ,  H05K1/021 ,  H05K2201/10106

Abstract: A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for controlLES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips.

Abstract translation: 公开了一种用于封装发光半导体（LES）的系统和方法。 提供了一种LES装置，其包括散热器和安装在散热器上并电连接到其上的LES芯片阵列，每个LES芯片包括连接焊盘和配置为响应于接收的电力从其发射光的发光区域。 LES装置还包括位于每个LES芯片上并电连接到每个LES芯片以提供LES芯片阵列的控制操作的柔性互连结构，其中柔性互连结构还包括被配置为符合散热器形状的柔性介电膜 以及金属互连结构，其形成在柔性电介质膜上并且延伸穿过形成在柔性电介质膜中的通孔，以便电连接到LES芯片的连接焊盘。

公开(公告)号：US20140138807A1

公开(公告)日：2014-05-22

申请号：US14165725

申请日：2014-01-28

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee

IPC: H01L23/495

CPC classification number: H01L23/495 ,  H01L21/50 ,  H01L23/3735 ,  H01L23/49531 ,  H01L23/49575 ,  H01L23/49811 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.

公开(公告)号：US20240266270A1

公开(公告)日：2024-08-08

申请号：US18166192

申请日：2023-02-08

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Ljubisa D. Stevanovic ,  Christopher James Kapusta ,  Robert Dwayne Gossman ,  Risto Ilkka Sakari Tuominen

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/49861

Abstract: A semiconductor assembly includes a semiconductor device and a POL-RDL package coupled to said device. The device includes an upper surface, a gate pad and at least one source pad disposed on said upper surface. The POL-RDL package includes a dielectric layer having at least one source pad electrically coupled to said at least one source pad of said device and at least one contact pad disposed. At least one trace connection having a resistivity value electrically couples said at least one source pad of said POL-RDL package to said at least one contact pad.

公开(公告)号：USRE48015E1

公开(公告)日：2020-05-26

申请号：US15886478

申请日：2018-02-01

Applicant: General Electric Company

Inventor： Gamal Refai-Ahmed ,  David Mulford Shaddock ,  Arun Virupaksha Gowda ,  John Anthony Vogel ,  Christian Michael Giovanniello

IPC: H01L33/02 ,  H01L25/16 ,  H01L25/00 ,  H01L33/62 ,  H01L33/64 ,  H01L33/54 ,  H01S5/022 ,  H01S5/024 ,  H01L23/538

Abstract: An electronic packaging assembly having a semiconductor integrated circuit and a plurality of interconnect components is provided. The plurality of interconnect components is operatively coupled to the semiconductor integrated circuit. Further, one or more interconnect components include one or more support elements having a first surface and a second surface, and one or more spring elements having a first end and a second end, and wherein first ends of the one or more spring elements are coupled to the first surface or the second surface of a respective support element.

公开(公告)号：US10269688B2

公开(公告)日：2019-04-23

申请号：US13897685

申请日：2013-05-20

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/34 ,  H01L23/495 ,  H01L23/433 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

公开(公告)号：US10186477B2

公开(公告)日：2019-01-22

申请号：US15363237

申请日：2016-11-29

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/495 ,  H01L23/433 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

公开(公告)号：US10070531B2

公开(公告)日：2018-09-04

申请号：US14579569

申请日：2014-12-22

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Donald Paul Cunningham ,  Shakti Singh Chauhan

IPC: H01L33/00 ,  H05K1/18 ,  H01L25/075 ,  H01L33/62 ,  H01L27/15 ,  H01L33/60 ,  H01L33/64 ,  H05K1/02

Abstract: A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for control LES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips.