公开(公告)号：US09627535B2

公开(公告)日：2017-04-18

申请号：US15055805

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Min Gyu Sung

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: A device includes a gate structure having an axial length that is positioned above an active region of a semiconductor substrate and includes a first gate structure portion positioned above the active region and second gate structure portions positioned above an isolation region formed in the semiconductor substrate. An etch stop layer is positioned on the gate structure and covers sidewall surfaces of the second gate structure portions but does not cover any sidewall surfaces of the first gate structure portion. First and second contact trenches extend continuously along the first gate structure portion for less than the axial length of the gate structure and are positioned above at least a portion of the active region on respective opposing first and second sides of the gate structure. An epi semiconductor material is positioned on the active region within each of the first and second contact trenches.

公开(公告)号：US09589850B1

公开(公告)日：2017-03-07

申请号：US14964746

申请日：2015-12-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Kisup Chung ,  Sivananda Kanakasabapathy

IPC: H01L21/8238 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/823456 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/4966

Abstract: Controlled recessing of materials in cavities and resulting devices are disclosed. Embodiments include providing a dielectric layer over first-type and second-type transistor regions, and long and short channel-cavities in the dielectric in each transistor region; conformally forming a gate dielectric layer in the long and short channel-cavities, and on an upper surface of the dielectric; conformally forming a first-type work-function metal layer on the gate dielectric; forming a block-mask over the first-type transistor region; removing the first-type work-function metal from the second-type transistor region; removing the block-mask; conformally forming a second-type work-function metal on all exposed surfaces; forming a metal barrier layer on exposed surfaces and filling the short channel-cavities; filling the long channel-cavities with a conductive material; planarizing all layers down to the upper surface of the dielectric; and applying a tilted ion beam to recess the gate dielectric, first and second type work-function metal, and metal barrier layers.

Abstract translation: 公开了空腔和结果装置中材料的受控凹陷。 实施例包括在第一类型和第二类型晶体管区域上提供介电层，以及在每个晶体管区域中的电介质中的长和短沟道腔; 在长和短通道腔中保形地形成栅极电介质层，并在电介质的上表面上形成栅介电层; 在栅极电介质上保形地形成第一型功函数金属层; 在所述第一型晶体管区域上形成块掩模; 从第二类型晶体管区域去除第一类型功函数金属; 去除阻挡掩模; 在所有暴露的表面上保形地形成第二种功能金属; 在暴露的表面上形成金属阻挡层并填充短沟槽; 用导电材料填充长通道腔; 将所有层平坦化到电介质的上表面; 并且施加倾斜的离子束以使所述栅极电介质，第一和第二类型功函数金属以及金属阻挡层凹陷。

公开(公告)号：US20170047253A1

公开(公告)日：2017-02-16

申请号：US14822340

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L21/768 ,  H01L21/311 ,  H01L29/66 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/76897 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76837 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2221/1026 ,  H01L2221/1036

Abstract: One illustrative method disclosed includes, among other things, forming a silicon dioxide etch stop layer on and in contact with a source/drain region and adjacent silicon nitride sidewall spacers positioned on two laterally spaced-apart transistors having silicon dioxide gate cap layers, performing a first etching process through an opening in a layer of insulating material to remove the silicon nitride material positioned above the source/drain region, performing a second etching process to remove a portion of the silicon dioxide etch stop layer and thereby expose a portion of the source/drain region, and forming a conductive self-aligned contact that is conductively coupled to the source/drain region.

Abstract translation: 所公开的一种示例性方法包括在源极/漏极区域上形成二氧化硅蚀刻停止层并与源极/漏极区域接触的相邻的氮化硅侧壁间隔物，其位于具有二氧化硅栅极盖层的两个横向间隔开的晶体管上， 通过绝缘材料层中的开口进行第一蚀刻工艺，以去除位于源/漏区域上方的氮化硅材料，执行第二蚀刻工艺以去除二氧化硅蚀刻停止层的一部分，从而暴露出源的一部分 /漏极区域，并且形成导电地与源极/漏极区域耦合的导电自对准接触。

公开(公告)号：US20170012107A1

公开(公告)日：2017-01-12

申请号：US14795984

申请日：2015-07-10

Applicant: GLOBALFOUNDRIES, INC. ,  International Business Machines Corporation

Inventor： Chanro Park ,  Injo Ok

IPC: H01L29/49 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/70 ,  H01L21/82 ,  H01L21/82345 ,  H01L21/823456 ,  H01L29/66545

Abstract: Integrated circuits and methods for producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a work function layer overlying a substrate and a plurality of dielectric columns. The dielectric columns and the substrate define a short region having a short region width and a long region having a long region width greater than the short region width. The work function layer is recessed in the long region to a long region work function height that is between a dielectric column top surface and a substrate top surface. The work function layer is also recessed in the short region to a short region work function height that is between the dielectric column top surface and the substrate top surface. Recessing the work function layer in the long and short regions is conducted in the absence of lithography techniques.

Abstract translation: 提供了集成电路及其制造方法。 在示例性实施例中，用于制造集成电路的方法包括形成覆盖在基板和多个电介质柱上的功函数层。 电介质柱和衬底限定具有短区域宽度的短区域和具有大于短区域宽度的长区域宽度的长区域。 工作功能层在长区域中凹陷到介电柱顶表面和基板顶表面之间的长区域功函数高度。 工作功能层也在短区域中凹陷到介电柱顶表面和衬底顶表面之间的短区域功函数高度。 在没有光刻技术的情况下，在长和短区域内嵌入功函数层。

公开(公告)号：US09461171B2

公开(公告)日：2016-10-04

申请号：US14283636

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hoon Kim ,  Naim Moumen ,  Chanro Park ,  William J. Taylor, Jr.

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76805 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, performing an epitaxial deposition process to form an epi semiconductor material on the active region in the source/drain region of the device, performing an etching process on the epi semiconductor material to remove a portion of the epi semiconductor material so as to define at least one epi recess in the epi semiconductor material, forming a metal silicide layer on the upper surface of the epi semiconductor material and in the at least one epi recess in the epi semiconductor material, and forming a conductive structure that is conductively coupled to the metal silicide layer.

Abstract translation: 所公开的一种方法包括在半导体衬底的有源区上方形成栅极结构，执行外延沉积工艺以在器件的源极/漏极区域中的有源区上形成外延半导体材料，进行蚀刻 处理外延半导体材料以去除外延半导体材料的一部分，以便限定外延半导体材料中的至少一个外延凹部，在外延半导体材料的上表面上形成金属硅化物层，并且在至少一个 epi凹槽，并且形成导电耦合到金属硅化物层的导电结构。

公开(公告)号：US09391174B1

公开(公告)日：2016-07-12

申请号：US14730735

申请日：2015-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Hoon Kim

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/3083

Abstract: Uniform fin recessing for the situation of recessing nonadjacent fins and the situation of recessing adjacent fins includes providing a starting semiconductor structure, the structure including a semiconductor substrate, multiple fins coupled to the substrate, each fin having a hard mask layer thereover and being surrounded by isolation material. The hard mask layer is then removed over some of the fins, at least partially removing the some of the raised structures, the at least partially removing creating openings, and filling the openings with an optical planarization layer (OPL) material.

Abstract translation: 针对不相邻散热片的凹陷状况的均匀的翅片凹陷以及相邻散热片的凹陷情况包括提供起始半导体结构，该结构包括半导体衬底，耦合到衬底的多个鳍片，每个散热片具有其上的硬掩模层并被 隔离材料。 然后在一些翅片上去除硬掩模层，至少部分地去除一些凸起结构，至少部分去除创建开口，并用光学平坦化层（OPL）材料填充开口。

公开(公告)号：US20160163601A1

公开(公告)日：2016-06-09

申请号：US14560102

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Sean Xuan Lin

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/823468 ,  H01L21/02181 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: A method that involves forming a high-k gate insulation layer, a work-function adjusting metal layer and a metal protection layer in first and second replacement gate cavities, wherein the metal protection layer is formed so as to pinch-off the first gate cavity while leaving the second gate cavity partially un-filled, forming a first bulk conductive metal layer in the un-filled portion of the second gate cavity, removing substantially all of the metal protection layer in the first gate cavity while leaving a portion of the metal protection layer in the second gate cavity, forming a second conductive metal layer within the first and second replacement gate cavities, recessing the conductive metal layers so as to define first and second gate-cap cavities in the first and second replacement gate cavities, respectively, and forming gate cap layers within the first and second gate-cap cavities.

Abstract translation: 一种涉及在第一和第二替换栅腔中形成高k栅极绝缘层，功函数调整金属层和金属保护层的方法，其中金属保护层形成为夹住第一栅极腔 同时使第二栅极腔部分未填充，在第二栅极腔的未填充部分中形成第一体导电金属层，基本上除去第一栅极腔中的所有金属保护层，同时留下金属的一部分 在所述第二栅极腔中形成保护层，在所述第一和第二替代栅极腔内形成第二导电金属层，使所述导电金属层凹陷，以分别在所述第一和第二替换栅极腔中限定第一和第二栅极盖腔， 以及在所述第一和第二栅极盖腔内形成栅极盖层。

公开(公告)号：US20160163585A1

公开(公告)日：2016-06-09

申请号：US14674460

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Andre Labonte

IPC: H01L21/768 ,  H01L29/45 ,  H01L29/417 ,  H01L21/283 ,  H01L29/66

CPC classification number: H01L21/76843 ,  H01L21/283 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66628

Abstract: One method disclosed includes, among other things, forming a structure comprised of an island of a first insulating material positioned between the gate structures above the source/drain region and under a masking layer feature of a patterned masking layer, forming a liner layer that contacts the island of insulating material and the masking layer feature, selectively removing the masking layer feature to thereby form an initial opening that is defined by the liner layer, performing at least one isotropic etching process through the initial opening to remove the island of first insulating material and thereby define a contact opening that exposes the source/drain region, and forming a conductive contact structure in the contact opening that is conductively coupled to the source/drain region.

Abstract translation: 所公开的一种方法包括形成由位于源/漏区之上的栅极结构之间的第一绝缘材料的岛和图案化掩模层的掩模层特征之下的一个结构，形成接触 绝缘材料岛和掩模层特征，选择性地去除掩模层特征，从而形成由衬里层限定的初始开口，通过初始开口进行至少一个各向同性蚀刻工艺以去除第一绝缘材料岛 从而限定暴露源极/漏极区域的接触开口，以及在与源极/漏极区域导电耦合的接触开口中形成导电接触结构。

公开(公告)号：US09362377B1

公开(公告)日：2016-06-07

申请号：US14633998

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Vimal Kamineni ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/44 ,  H01L23/52 ,  H01L29/49 ,  H01L21/28 ,  H01L21/285 ,  H01L21/321 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/32134 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Methods for forming a semiconductor gate electrode with a reflowed Co layer and the resulting device are disclosed. Embodiments include forming a trench in an ILD on a substrate; forming a high-k dielectric layer, a WF layer, and a Co layer sequentially on sidewall and bottom surfaces of the trench; reflowing a portion of the Co layer from the WF layer on the sidewall surfaces of the trench to the WF layer on the bottom surface of the trench; removing a remainder of the Co layer from the WF layer on the sidewall surfaces of the trench, above an upper surface of the reflowed Co; recessing the WF layer to the upper surface of the reflowed Co layer, forming a cavity above the reflowed Co layer; and filling the cavity with metal to form a gate electrode.

Abstract translation: 公开了用于形成具有回流Co层的半导体栅电极的方法和所得到的器件。 实施例包括在衬底上形成ILD中的沟槽; 在沟槽的侧壁和底表面上依次形成高k电介质层，WF层和Co层; 将Co层的一部分从沟槽的侧壁表面上的WF层回流到沟槽的底表面上的WF层; 从所述沟槽的侧壁表面上的所述WF层中除去所述Co层的剩余部分，在所述回流Co的上表面上方; 将WF层凹陷到回流Co层的上表面，在回流Co层上方形成空腔; 并用金属填充空腔以形成栅电极。

公开(公告)号：US20160049399A1

公开(公告)日：2016-02-18

申请号：US14865784

申请日：2015-09-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L21/28026 ,  H01L21/2807 ,  H01L21/283 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0928 ,  H01L27/105 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/772 ,  H01L29/7833 ,  H01L29/785

Abstract: One illustrative gate structure of a transistor device disclosed herein includes a high-k gate insulation layer and a work function metal layer positioned on the high-k gate insulation layer. The device further includes a first bulk metal layer positioned on the work function metal layer. The device further includes a second bulk metal layer. The first and second bulk metal layers have upper surfaces that are at substantially the same height level, and the first and second bulk metal layers are made of substantially the same material. The device further includes a conductive etch stop layer between the first and second bulk metal layers.

Abstract translation: 本文公开的晶体管器件的一个说明性栅极结构包括高k栅极绝缘层和位于高k栅极绝缘层上的功函数金属层。 该装置还包括位于功函数金属层上的第一体金属层。 该装置还包括第二体金属层。 第一和第二块体金属层具有基本上相同的高度水平的上表面，并且第一和第二块体金属层由基本上相同的材料制成。 该器件还包括在第一和第二块体金属层之间的导电蚀刻停止层。