公开(公告)号：US20190148373A1

公开(公告)日：2019-05-16

申请号：US15811961

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongiun Shi ,  Lei Sun ,  Laertis Economikos ,  Ruilong Xie ,  Lars Liebmann ,  Chanro Park ,  Daniel Chanemougame ,  Min Gyu Sung ,  Hsien-Ching Lo ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/762 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/0276 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.

公开(公告)号：US20190131433A1

公开(公告)日：2019-05-02

申请号：US15795879

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alina Vinslava ,  Hsien-Ching Lo ,  Yongjun Shi ,  Jianwei Peng ,  Jianghu Yan ,  Yi Qi

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.

公开(公告)号：US20190051735A1

公开(公告)日：2019-02-14

申请号：US15869349

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Xusheng Wu ,  Jianwei Peng ,  Sipeng Gu ,  Hsien-Ching Lo

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02

Abstract: Methods of forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed over a sacrificial layer. A support structure is connected with the semiconductor fin. After forming the support structure, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin. A semiconductor material is epitaxially grown in the cavity to form a source/drain region of the vertical-transport field-effect transistor.

公开(公告)号：US10121868B1

公开(公告)日：2018-11-06

申请号：US15585865

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Kwan-Yong Lim ,  Hui Zhan

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed includes, among other things, forming a gate around an initial fin structure and above a layer of insulating material, and performing a fin trimming process on an exposed portion of the initial fin structure in the source/drain region so as to produce a reduced-size fin portion positioned above a surface of a layer of insulating material in the source/drain region of the device, wherein the the reduced-size fin portion has a second size that is less than the first size. In this example, the method also includes forming a conformal epi semiconductor material on the reduced-size fin portion and forming a conductive source/drain contact structure that is conductively coupled to and wrapped around the conformal epi semiconductor material.

公开(公告)号：US10050125B1

公开(公告)日：2018-08-14

申请号：US15676300

申请日：2017-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hui Zang ,  Xusheng Wu ,  Hsien-Ching Lo

IPC: H01L29/76 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535 ,  H01L29/78 ,  H01L29/08

Abstract: Methods of forming a structure for a vertical-transport field-effect transistor and structures for a vertical-transport field-effect transistor. A semiconductor fin is formed on a sacrificial layer, and trench isolation is formed in which the semiconductor fin is embedded. The trench isolation is removed at opposite sidewalls of the semiconductor fin. After the trench isolation is removed at opposite sidewalls of the semiconductor fin, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin while the semiconductor fin is supported by the trench isolation adjacent to opposite end surfaces of the semiconductor fin. A semiconductor material is formed in the cavity to provide a source/drain region.

公开(公告)号：US20180190792A1

公开(公告)日：2018-07-05

申请号：US15397967

申请日：2017-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jianwei Peng ,  Hsien-Ching Lo ,  Suresh K. Regonda ,  Edward P. Reis, JR.

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/66636 ,  H01L21/3065 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

Abstract: The disclosure is directed to a semiconductor structure and method of forming same. The method including: implanting a species within a region of a substrate adjacent to a gate stack; forming a first spacer laterally adjacent to the gate stack over the substrate; and forming an opening within the implanted region of the substrate, the opening being substantially U-shaped and self-aligned with the first spacer. The semiconductor structure including: a fin; a gate stack substantially surrounding the fin; a first pair of spacers over the fin and laterally adjacent to the gate stack; and a pair of substantially U-shaped cavities within the fin and on opposing sides of the gate stack, the pair of substantially U-shaped cavities being self-aligned with the first pair of spacers, wherein the pair of substantially U-shaped cavities are filled with a source/drain material.

公开(公告)号：US20180151690A1

公开(公告)日：2018-05-31

申请号：US15875055

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tao Han ,  Zhenyu Hu ,  Jinping Liu ,  Hsien-Ching Lo ,  Jianwei Peng

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/0228 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.

公开(公告)号：US09887094B1

公开(公告)日：2018-02-06

申请号：US15585800

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng ,  Yanping Shen ,  Hui Zhan

IPC: H01L21/3105 ,  H01L29/66 ,  H01L29/08 ,  H01L21/311

CPC classification number: H01L21/31053 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: One illustrative method disclosed includes, among other things, forming a fin spacer adjacent a lower portion of a fin that is comprised of a fin spacer material, forming a conformal layer of a second spacer material on the exposed sidewalls and the upper surface of the fin, on the fin spacer and adjacent a gate structure of the FinFET device, wherein the second spacer material is a different material than the fin spacer material, performing an etching process to remove the second conformal layer from above the fin spacer to thereby re-expose the sidewalls of the fin above the fin spacer and the upper surface of the fin while forming a gate spacer comprising the second spacer material adjacent the gate structure, and forming an epi semiconductor material on the exposed sidewalls and upper surface of the fins above the first fin spacer.

公开(公告)号：US10546775B1

公开(公告)日：2020-01-28

申请号：US16052085

申请日：2018-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  Liu Jiang ,  Yongjun Shi ,  Yi Qi ,  Hsien-Ching Lo ,  Hui Zang

IPC: H01L21/70 ,  H01L21/768 ,  H01L27/12 ,  H01L29/66 ,  H01L21/28 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.

公开(公告)号：US20190341448A1

公开(公告)日：2019-11-07

申请号：US15968968

申请日：2018-05-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emilie M.S. Bourjot ,  Julien Frougier ,  Yi Qi ,  Ruilong Xie ,  Hui Zang ,  Hsien-Ching Lo ,  Zhenyu Hu

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L29/08

Abstract: Various aspects of the disclosure include nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, not just on the top and sides of the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects of the disclosure include nanosheet-FET structures having a bottom isolation to reduce parasitic S/D leakage to the substrate.