公开(公告)号：US09583640B1

公开(公告)日：2017-02-28

申请号：US14982028

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Sven Beyer ,  Carsten Grass ,  Tom Herrmann

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/7887 ,  H01L27/11531 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/665 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method comprises providing a semiconductor structure including a nonvolatile memory cell element comprising a floating gate, a select gate and an erase gate formed over a semiconductor material, the select gate and the erase gate being arranged at opposite sides of the floating gate, forming a control gate insulation material layer over the semiconductor structure, forming a control gate material layer over the control gate insulation material layer, performing a first patterning process that forms a control gate over the floating gate and comprises a first etch process that selectively removes a material of the control gate material layer relative to a material of the control gate insulation material layer, and performing a second patterning process that patterns the control gate insulation material layer, the patterned control gate insulation material layer covering portions of the semiconductor structure that are not covered by the control gate.

Abstract translation: 一种方法包括提供包括非易失性存储单元元件的半导体结构，所述非易失性存储单元元件包括在半导体材料上形成的浮置栅极，选择栅极和擦除栅极，所述选择栅极和擦除栅极被布置在所述浮置栅极的相对侧， 控制栅极绝缘材料层，在所述控制栅极绝缘材料层上方形成控制栅极材料层，执行在所述浮动栅极上形成控制栅极的第一图案化工艺，并且包括第一蚀刻工艺，所述第一蚀刻工艺选择性地去除 所述控制栅极材料层相对于所述控制栅极绝缘材料层的材料，并且执行对所述控制栅极绝缘材料层进行图案化的第二图案化工艺，所述图案化的控制栅极绝缘材料层覆盖所述半导体结构的不被 控制门。

公开(公告)号：US20170040450A1

公开(公告)日：2017-02-09

申请号：US14816337

申请日：2015-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Tom Hasche ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/06 ,  H01L27/12 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/66537 ,  H01L21/743 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7838 ,  H01L29/7843

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.

Abstract translation: 本公开根据一些说明性实施例提供了一种形成半导体器件的方法，所述方法包括提供SOI衬底，所述SOI衬底具有设置在掩埋绝缘材料层上的有源半导体层，所述有源半导体层又形成在基底衬底材料 在所述SOI衬底的有源区中的所述有源半导体层上形成栅极结构，在所述栅极结构形成之后，部分地露出所述基底以形成至少一个本体暴露区域，以及形成用于使所述至少一个 体积暴露区域。

公开(公告)号：US20150200140A1

公开(公告)日：2015-07-16

申请号：US14153521

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Alexander Ebermann ,  Carsten Grass ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/0275 ,  H01L21/28123 ,  H01L21/28176 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/823437 ,  H01L21/845

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate with a pad layer overlying the semiconductor substrate and a photoresist layer overlying the pad layer, exposing the photoresist layer to a split laser beam to form a plurality of parallel linear void regions in the photoresist layer, and etching the pad layer and the semiconductor substrate beneath the plurality of parallel linear void regions to form a plurality of extended parallel linear void regions. The method further includes depositing a first dielectric material over the semiconductor substrate, patterning a photoresist material over the semiconductor substrate to cover a portion of the semiconductor substrate, and etching portions of the pad layer, the first dielectric material, and the semiconductor substrate. Still further, the method includes depositing a second dielectric material into the second void regions.

Abstract translation: 一种用于制造集成电路的方法包括：提供具有覆盖在半导体衬底上的衬垫层的半导体衬底和覆盖衬垫层的光致抗蚀剂层，将光致抗蚀剂层暴露于分裂激光束以在光刻胶中形成多个平行的线性空隙区域 并且在所述多个平行线性空隙区域下方蚀刻所述衬垫层和所述半导体衬底，以形成多个延伸的平行线性空隙区域。 该方法还包括在半导体衬底上沉积第一介电材料，在半导体衬底上图案化光致抗蚀剂材料以覆盖半导体衬底的一部分，以及蚀刻衬垫层，第一电介质材料和半导体衬底的部分。 此外，该方法包括将第二电介质材料沉积到第二空隙区域中。

公开(公告)号：US09054207B2

公开(公告)日：2015-06-09

申请号：US13937600

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Sven Beyer ,  Uwe Griebenow ,  Jan Hoentschel

IPC: H01L29/788 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L29/788 ,  G11C16/0425 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.

Abstract translation: 可以在自对准电荷存储区域的基础上提供用于半导体器件中的闪存区域的存储晶体管。 为此，可以在一些说明性实施例中提供浮动间隔元件，而在其他情况下，在替换栅极方法期间，电荷存储区域可以以自对准方式有效地嵌入电极材料中。 因此，可以不再需要用于图案化电荷存储区域的附加复杂光刻工艺，可以实现增强的位密度。

公开(公告)号：US20130273729A1

公开(公告)日：2013-10-17

申请号：US13888753

申请日：2013-05-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Klaus Hempel ,  Sven Beyer ,  Markus Lenski ,  Stephan Kruegel

IPC: H01L21/28

CPC classification number: H01L21/28088 ,  H01L21/28026 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833 ,  H01L29/7843

Abstract: In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.

Abstract translation: 在替代浇口方法中，可以通过在去除占位材料的中间状态下进行材料侵蚀过程来实现闸门开口的优越的横截面形状。 因此，当执行拐角舍入处理顺序时，占位符材料的剩余部分可以有效地保护诸如高k电介质材料的底层敏感材料。

公开(公告)号：US10283490B2

公开(公告)日：2019-05-07

申请号：US15713064

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L25/16 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/04

Abstract: A method includes forming a stack of semiconductor die. The stack includes a first semiconductor die, a second semiconductor die and a third semiconductor die. The first semiconductor die is stacked above the second semiconductor die and the third semiconductor die is stacked above the first semiconductor die. A first optical transmitter and a first optical receiver are provided in the first semiconductor die, a second optical transmitter is provided in the second semiconductor die, and a second optical receiver is provided in the third semiconductor die. A first optical signal is transmitted from the first optical transmitter in the first semiconductor die to the second optical receiver in the third semiconductor die. A second optical signal is transmitted from the second optical transmitter in the second semiconductor die to the first optical receiver in the first semiconductor die.

公开(公告)号：US10249633B2

公开(公告)日：2019-04-02

申请号：US15831833

申请日：2017-12-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Sven Beyer ,  Jan Paul

IPC: H01L27/12 ,  H01L29/423 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531

Abstract: An integrated circuit product includes a silicon-on-insulator (SOI) substrate and a flash memory device positioned in a first area of the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulating layer positioned above the semiconductor bulk substrate, and a semiconductor layer positioned above the buried insulating layer, and the flash memory device includes a flash transistor device and a read transistor device. The flash transistor device includes a floating gate, an insulating layer positioned above the floating gate, and a control gate positioned above the insulating layer, wherein the floating gate includes a portion of the semiconductor layer. The read transistor device includes a gate dielectric layer positioned above the semiconductor bulk substrate and a read gate electrode positioned above the gate dielectric layer.

公开(公告)号：US20180366484A1

公开(公告)日：2018-12-20

申请号：US15622497

申请日：2017-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Jochen Willi. Poth ,  Sven Beyer ,  Stefan Duenkel ,  Sandhya Chandrashekhar ,  Zhi-Yuan Wu

IPC: H01L27/11568 ,  H01L29/06 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/78648 ,  H01L29/792

Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.

公开(公告)号：US10157996B2

公开(公告)日：2018-12-18

申请号：US15648889

申请日：2017-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Jan Hoentschel ,  Nigel Chan ,  Sven Beyer

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.

公开(公告)号：US09793372B1

公开(公告)日：2017-10-17

申请号：US15163806

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Jan Hoentschel ,  Nigel Chan ,  Sven Beyer

IPC: H01L29/49 ,  H01L29/66 ,  H01L27/12 ,  H01L29/78 ,  H01L21/308 ,  H01L21/306 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L21/84

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/7831

Abstract: An integrated circuit includes a first transistor, a second transistor and a dummy gate structure. The first transistor includes a first gate structure. The first gate structure includes a first gate insulation layer including a high-k dielectric material and a first gate electrode. The second transistor includes a second gate structure. The second gate structure includes a second gate insulation layer including the high-k dielectric material and a second gate electrode. The dummy gate structure is arranged between the first transistor and the second transistor and substantially does not include the high-k dielectric material.