公开(公告)号：US20180269297A1

公开(公告)日：2018-09-20

申请号：US15461634

申请日：2017-03-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan ZHANG ,  Frank MONT ,  Mark RAYMOND ,  Chengyu NIU

IPC: H01L29/45 ,  H01L29/66 ,  H01L21/28 ,  H01L29/08 ,  H01L21/768 ,  H01L21/285 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L29/45 ,  H01L21/28008 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76877 ,  H01L21/76889 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7851

Abstract: A conductive source/drain contact is formed within a trench overlying a raised epitaxial source/drain junction. The conductive contact includes a conductive liner and a conductive fill material formed directly over the conductive liner. The conductive fill material is selected from a platinum group metal such as ruthenium. The conductive liner may be directionally deposited into the trench and is adapted to form a metal silicide in situ through a reaction with the epitaxial layer.

公开(公告)号：US20180144976A1

公开(公告)日：2018-05-24

申请号：US15360255

申请日：2016-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shao Beng LAW ,  Xunyuan ZHANG ,  Frank W. MONT ,  Genevieve BEIQUE ,  Lei SUN

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/285

CPC classification number: H01L21/76816 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32051 ,  H01L21/76877 ,  H01L23/5283

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to post spacer self-aligned cut structures and methods of manufacture. The method includes: providing a non-mandrel cut; providing a mandrel cut; forming blocking material on underlying conductive material in the non-mandrel cut and the mandrel cut; forming trenches with the blocking material acting as a blocking mask at the mandrel cut and the non-mandrel cut; and filling the trenches with metallization features such that the metallization features have a tip to tip alignment.

公开(公告)号：US20180012887A1

公开(公告)日：2018-01-11

申请号：US15202764

申请日：2016-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre LABONTE ,  Ruilong XIE ,  Xunyuan ZHANG

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/45 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/78 ,  H01L21/3105

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53209 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the core. The liner is etched to the level of the TS. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core at a shelf portion of the CB trench. The core is etched to extend the CB trench to a bottom at the gate metal. The shelf portion having a larger area than the bottom. The CB trench is metalized to form a CB contact.

公开(公告)号：US20160260605A1

公开(公告)日：2016-09-08

申请号：US15154444

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi QI ,  Xunyuan ZHANG ,  Catherine B. LABELLE

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L21/02532 ,  H01L21/02639 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench.

公开(公告)号：US20150137273A1

公开(公告)日：2015-05-21

申请号：US14080842

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan ZHANG ,  Xiuyu CAI ,  Hoon KIM

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76856 ,  H01L21/76897 ,  H01L29/4958 ,  H01L29/6653 ,  H01L29/78

Abstract: A methodology for forming a self-aligned contact (SAC) that exhibits reduced likelihood of a contact-to-gate short circuit failure and the resulting device are disclosed. Embodiments may include forming a replacement metal gate, with spacers at opposite sides thereof, on a substrate, forming a recess in an upper surface of the spacers along outer edges of the replacement metal gate, and forming an aluminum nitride (AlN) cap over the metal gate and in the recess.

Abstract translation: 公开了一种用于形成展现出接触到栅极短路故障的可能性降低的自对准接触（SAC）的方法以及所得到的器件。 实施例可以包括在衬底上形成具有相对侧面的间隔物的替换金属栅极，在替代金属栅极的外边缘上在间隔物的上表面中形成凹部，并在该金属栅极上形成氮化铝（AlN） 金属门和凹槽。

公开(公告)号：US20140353835A1

公开(公告)日：2014-12-04

申请号：US13903283

申请日：2013-05-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Moosung M. CHAE ,  Errol Todd RYAN ,  Nicholas Vincent LICAUSI ,  Christian WITT ,  Ailian ZHAO ,  Ming HE ,  Sean X. LIN ,  Xunyuan ZHANG ,  Kunaljeet TANWAR

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76831 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76843 ,  H01L2221/1047

Abstract: A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.

Abstract translation: 提供了一种用于在半导体制造期间减少超低k层的自形成势垒的污染的方法的方法。 一方面，一种方法包括：提供包含至少一个沟槽的固化的超低k膜，并且用孔填充材料填充膜的孔; 在沟槽的表面去除暴露的孔隙填充材料以形成暴露的孔; 并在沟槽的表面上形成自形成阻挡层。