公开(公告)号：US09947532B2

公开(公告)日：2018-04-17

申请号：US15425338

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson R. Holt ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa A. Smith

IPC: H01L21/00 ,  H01L21/20 ,  H01L21/02 ,  H01L21/76 ,  H01L29/06 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/762

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02636 ,  H01L21/02647 ,  H01L21/2022 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76248 ,  H01L21/76294 ,  H01L29/0642 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device can include the following steps: (i) providing an initial sub-assembly including a trench-defining layer having a top surface; (ii) refining the initial sub-assembly into a first trench-cut intermediate sub-assembly by removing material to form an upper tier of a trench extending downward from the top surface of the trench-defining layer, the upper tier of the trench including two lateral trench surfaces and a bottom trench surface; and (iii) refining the first trench-cut intermediate sub-assembly into a second trench-cut intermediate sub-assembly by selectively removing material in a downwards direction starting from the bottom surface of the trench to form a lower tier of the trench, with the selective removal of material leaving at least a first defect blocking member in the lower tier of the trench.

公开(公告)号：US09634142B1

公开(公告)日：2017-04-25

申请号：US15076699

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dominic J. Schepis ,  Alexander Reznicek ,  Pouya Hashemi ,  Kangguo Cheng

IPC: H01L21/324 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: A method may include forming a germanium-including fin on a substrate, and forming a dummy gate extending over the germanium-including fin, creating a channel under the gate and a source/drain region of the germanium-including fin extending from under the dummy gate on each side of the dummy gate. An in-situ p-type doped silicon germanium layer may be grown over the source/drain region, the germanium-including fin having a higher concentration of germanium than the in-situ p-type doped silicon germanium layer. An anneal thermally mixes the germanium of the in-situ p-type doped silicon germanium layer and the germanium of the germanium-including fin in the source/drain region of the germanium-including fin and diffuses the p-type dopant of the in-situ p-type doped silicon germanium layer into the channel of the germanium-including fin, forming a source/drain extension. A portion of the channel has a higher germanium concentration than the source/drain region.

公开(公告)号：US09525027B2

公开(公告)日：2016-12-20

申请号：US14208518

申请日：2014-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Pouya Hashemi ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/84 ,  H01L29/10 ,  H01L29/66 ,  H01L29/735 ,  H01L21/225 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L29/1008 ,  H01L21/2254 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0924 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/4232 ,  H01L29/6625 ,  H01L29/66795 ,  H01L29/735 ,  H01L29/785

Abstract: A lateral bipolar junction transistor is fabricated using a semiconductor-on-insulator substrate. The transistor includes a germanium gradient within a doped silicon base region, there being an increasing germanium content in the direction of the collector region of the transistor. The use of a substrate including parallel silicon fins to fabricate lateral bipolar junction transistors facilitates the inclusion of both CMOS FinFET devices and lateral bipolar junction transistors having graded silicon germanium base regions on the same chip.

Abstract translation: 使用绝缘体上半导体衬底制造横向双极结晶体管。 晶体管包括在掺杂硅基区内的锗梯度，晶体管的集电极区域的方向上锗含量增加。 使用包括平行硅散热片的衬底来制造横向双极结晶体管有助于将CMOS FinFET器件和具有分级硅锗基极区域的横向双极结型晶体管包括在同一芯片上。

公开(公告)号：US09466616B2

公开(公告)日：2016-10-11

申请号：US15054951

申请日：2016-02-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric C. T. Harley ,  Judson R. Holt ,  Yue Ke ,  Timothy J. McArdle ,  Shogo Mochizuki ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.

公开(公告)号：US20160268413A1

公开(公告)日：2016-09-15

申请号：US14641917

申请日：2015-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Eric C. T. Harley ,  Yue Ke ,  Alexander Reznicek ,  Henry K. Utomo

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/306 ,  H01L29/04 ,  H01L29/45 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a fin upon a semiconductor substrate. A clean epitaxial growth surface is provided by forming a buffer layer upon fin sidewalls and an upper surface of the fin. The buffer layer may be epitaxially grown. Diamond shaped epitaxy is grown from the buffer layer sidewalls. In some implementations, the diamond shaped epitaxy may be subsequently merged with surrounding dielectric. A dopant concentration of the surrounding dielectric may be higher than a dopant concentration of the diamond shaped epitaxy.

Abstract translation: 半导体结构包括半导体衬底上的翅片。 通过在翅片侧壁和翅片的上表面上形成缓冲层来提供干净的外延生长表面。 缓冲层可以外延生长。 菱形外延从缓冲层侧壁生长。 在一些实施方案中，钻石形外延可以随后与周围的电介质合并。 周围电介质的掺杂剂浓度可高于菱形外延的掺杂剂浓度。

公开(公告)号：US20160268123A1

公开(公告)日：2016-09-15

申请号：US14645449

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/207 ,  H01L29/10 ,  H01L29/36

CPC classification number: H01L29/16 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02538 ,  H01L21/02658 ,  H01L29/36

Abstract: A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the III-V layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.

Abstract translation: 一种在多孔半导体结构上形成半导体的方法。 该方法可以包括形成堆叠，堆叠包括（从底部到顶部）衬底，基底硅层，厚硅层和薄硅层，其中薄硅层和厚硅层被松弛; 使用多孔化方法将厚硅层转化为多孔硅层; 在薄硅层上形成III-V层，III-V层被松弛，薄硅层变形，多孔硅层部分变形。

公开(公告)号：US09406545B2

公开(公告)日：2016-08-02

申请号：US14735466

申请日：2015-06-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L27/12 ,  H01L27/108 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/7621 ,  H01L21/76205 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7851

Abstract: A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices.

公开(公告)号：US09324795B2

公开(公告)日：2016-04-26

申请号：US14751493

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

公开(公告)号：US09299777B2

公开(公告)日：2016-03-29

申请号：US14751706

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

公开(公告)号：US09287264B1

公开(公告)日：2016-03-15

申请号：US14561395

申请日：2014-12-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Eric C. T. Harley ,  Judson R. Holt ,  Gauri V. Karve ,  Yue Ke ,  Derrick Liu ,  Timothy J. McArdle ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa A. Smith

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/84 ,  H01L29/36 ,  H01L29/20 ,  H01L29/16 ,  H01L27/12

CPC classification number: H01L27/0924 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.

Abstract translation: 本发明的实施例提供了一种外延生长FinFET的方法。 一种方法可以包括提供包括绝缘体和底层的半导体衬底; 使用外延生长在所述半导体衬底上形成沟道层; 将凹槽蚀刻到沟道层中并外延地再生沟道层上的一部分; 蚀刻通道层和底层以形成翅片; 形成栅极结构和一组间隔物; 将源漏区蚀刻到沟道层中; 以及在源极漏极区域中形成源极漏极材料。