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62 条记录 (耗时 0.019 秒)

    Cable harness forming machine comprising wire feed-out means in harness laying head
    21.
    发明授权
    Cable harness forming machine comprising wire feed-out means in harness laying head 失效
    线束成型机，包括线束敷设头中的送丝装置

    公开(公告)号：US3947943A

    公开(公告)日：1976-04-06

    申请号：US485034

    申请日：1974-07-01

    申请人： Takamasa Kokubo ,  Mikio Sakai ,  Tomohide Inada ,  Takashi Nakanishi ,  Hiroshi Seki ,  Hazime Yaegashi ,  Kouji Izumi ,  Morio Matsumura ,  Takao Nomura ,  Hisakazu Kato

    发明人： Takamasa Kokubo ,  Mikio Sakai ,  Tomohide Inada ,  Takashi Nakanishi ,  Hiroshi Seki ,  Hazime Yaegashi ,  Kouji Izumi ,  Morio Matsumura ,  Takao Nomura ,  Hisakazu Kato

    IPC分类号： H01B13/012 ,  H01R43/00 ,  H01B13/00

    CPC分类号： H01B13/01245 ,  Y10T29/5177 ,  Y10T29/53004 ,  Y10T29/53243

    摘要： A machine comprises a wire station for supplying various wires, a harness board on which a cable harness is to be formed, and a harness laying head movable relative to the harness board for receiving selected one of the wires from the wire station laying the selected wire on the harness board. The wire station comprises a plurality of wire clampers for releasably clamping the respective wires with their free ends protruding approximately a predetermined length towards the harness laying head. The head comprises a wire feed-in station operable in its wire released mode of receiving therein the selected wire and in its wire take-up made of taking up the wire received therein, a wire storing station for storing the taken-up wire therein, a wire feed-out station operable in its wire driving mode of positively driving the stored wire to the outside of the head and in its wire holding mode of immovably holding the selected wire, a cutter for cutting the wire held by the feed-out station into a first section having a trailing end in the head and a second section having a leading end also in the head, and a wire pusher for pushing the trailing end substantially out of the head.

    摘要翻译： 一种机器包括用于提供各种电线的线路站，将要在其上形成电缆线束的线束板以及可相对于线束板移动的线束布置头，用于从敷设所选线材的线路站接收选定的一条电线 在线束板上。 线路站包括多个线夹具，用于可释放地夹紧相应的线，其自由端朝着线束敷设头大约预定长度突出。 磁头包括一个电线馈入电台，其电线释放模式可以在其中接收所选择的电线，并且在其接收由其中接收的电线构成的电线吸收中，一个用于将牵引电线存放在其中的电线存储台， 电线送出站，其电线驱动模式可操作地将存储的电线主动地驱动到磁头的外部，并且以不可移动地保持所选择的电线的电线保持模式，用于切割由馈送站保持的电线的切割器 进入具有在头部中的后端的第一部分和在头部中具有前端的第二部分，以及用于将后端基本上推出头部的丝线推动器。

    Memory Device and Semiconductor Integrated Circuit
    23.
    发明申请
    Memory Device and Semiconductor Integrated Circuit 有权
    存储器件和半导体集成电路

    公开(公告)号：US20080212359A1

    公开(公告)日：2008-09-04

    申请号：US11883653

    申请日：2006-04-21

    申请人： Shunsaku Muraoka ,  Koichi Osano ,  Satoru Mitani ,  Hiroshi Seki

    发明人： Shunsaku Muraoka ,  Koichi Osano ,  Satoru Mitani ,  Hiroshi Seki

    IPC分类号： G11C11/21

    CPC分类号： H01L27/1021 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/55 ,  G11C2213/56 ,  G11C2213/72 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

    摘要： First electrode layer includes a plurality of first electrode lines (W1, W2) extending parallel to each other. State-variable layer lying on the first electrode layer includes a plurality of state-variable portions (60-11, 60-12, 60-21, 60-22) which exhibits a diode characteristic and a variable-resistance characteristic. Second electrode layer lying on the state-variable layer includes a plurality of second electrode lines (B1, B2) extending parallel to each other. The plurality of first electrode lines and the plurality of second electrode lines are crossing each other when seen in a layer-stacking direction with the state-variable layer interposed therebetween. State-variable portion (60-11) is provided at an intersection of the first electrode line (W1) and the second electrode line (B1) between the first electrode line and the second electrode line.

    摘要翻译： 第一电极层包括彼此平行延伸的多个第一电极线（W 1，W 2）。 位于第一电极层上的状态变化层包括多个具有二极管特性和可变电阻特性的状态变化部分（60-11,60-12,60-21,60-22）。 位于状态变化层上的第二电极层包括彼此平行延伸的多个第二电极线（B 1，B 2）。 多个第一电极线和多个第二电极线在层叠方向观察时彼此交叉，其间置有状态变化层。 在第一电极线和第二电极线之间的第一电极线（W 1）和第二电极线（B 1）的交叉点处设置状态可变部分（60-11）。

    Vehicle water drainage structure
    24.
    发明申请
    Vehicle water drainage structure 有权
    车辆排水结构

    公开(公告)号：US20070007797A1

    公开(公告)日：2007-01-11

    申请号：US11480550

    申请日：2006-07-05

    申请人： Hiroshi Seki

    发明人： Hiroshi Seki

    IPC分类号： B60R27/00

    CPC分类号： B60H1/3233

    摘要： A water drainage structure is provided to prevent drainage water from getting on hot components inside the engine compartment and suppress the occurrence of evaporation noise. At least one water drainage opening is provided in a bottom portion of a vehicle member arranged on the under surface of a floor panel of a vehicle. The downstream end portion of a water drainage pipe is arranged to communicate with the inside of a closed cross sectional structure formed by the floor panel and the vehicle member. Drainage water from a vehicle device flows out of the downstream end portion of the water drainage pipe and is discharged to the outside of the vehicle through the water drainage openings of the vehicle member. As a result, the drainage water is prevented from getting on hot components inside the engine compartment of the vehicle and the occurrence of evaporation noise is suppressed.

    摘要翻译： 提供排水结构，以防止排水从发动机舱内的热部件上排出，并抑制蒸发噪音的发生。 至少一个排水口设置在布置在车辆底板的下表面上的车辆构件的底部中。 排水管的下游端部布置成与由地板镶板和车辆构件形成的封闭横截面结构的内部连通。 来自车辆装置的排水从排水管的下游端部流出，并通过车辆部件的排水口排出到车辆的外部。 结果，能够防止排水在车内的发动机室内发热，能够抑制蒸发噪音的发生。

    Semiconductor integrated circuit that handles the input/output of a signal with an external circuit
    25.
    发明授权
    Semiconductor integrated circuit that handles the input/output of a signal with an external circuit 有权
    用于处理具有外部电路的信号的输入/输出的半导体集成电路

    公开(公告)号：US07126859B2

    公开(公告)日：2006-10-24

    申请号：US10853007

    申请日：2004-05-25

    申请人： Hiroshi Seki

    发明人： Hiroshi Seki

    IPC分类号： G11C16/04

    CPC分类号： H01L27/092 ,  H03K19/00315

    摘要： A semiconductor integrated circuit that handles the input/output of a signal with an external circuit. The circuit includes a transistor transmitting a signal between the external circuit and an internal circuit with a drain/source therebetween at a given gate voltage. A first gate voltage supply circuit supplies a voltage at the gate of the transistor when supplied with a first power voltage at a first level of a control signal. A second gate voltage supply circuit supplies a voltage at the gate of the transistor when supplied with a second power voltage that is lower than the first power voltage at a second level of a control signal.

    摘要翻译： 一种用外部电路处理信号的输入/输出的半导体集成电路。 电路包括在给定的栅极电压下在外部电路和内部电路之间传输信号的晶体管，其中漏极/源极之间的信号。 第一栅极电压供应电路在被提供有控制信号的第一电平的第一电源电压时，提供在晶体管的栅极处的电压。 第二栅极电压供应电路在被提供具有低于控制信号的第二电平处的第一电源电压的第二电源电压时，在晶体管的栅极处提供电压。

    Semiconductor integrated circuit
    26.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US06861724B2

    公开(公告)日：2005-03-01

    申请号：US10647529

    申请日：2003-08-26

    申请人： Hiroshi Seki

    发明人： Hiroshi Seki

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H03K17/687 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H01L29/00

    CPC分类号： H03K19/018521

    摘要： The invention provides an integrated circuit that permits input of a signal of a potential which is higher than a power supply voltage supplied to an interface circuit and also higher than a maximum rated voltage allowable for a gate electrode of a transistor forming an interface circuit, even in a non-access mode. The invention can include a gate voltage control circuit that produces a gate voltage to be applied to a gate electrode of a transfer gate which is connected between an external input terminal and an input end of an input buffer and transmits an external signal input from the external input terminal to the input end of the input buffer. The gate voltage control circuit outputs, as the gate voltage, a voltage produced based on a relatively high first voltage to be applied as a power supply voltage of a semiconductor integrated circuit in the access mode while outputting, as the gate voltage, a voltage produced based on a relatively low second voltage to be applied as a power supply voltage of the semiconductor integrated circuit in the non-access mode.

    摘要翻译： 本发明提供了一种集成电路，其允许输入高于提供给接口电路的电源电压的电位信号，并且还高于形成接口电路的晶体管的栅电极允许的最大额定电压，甚至 处于非访问模式。 本发明可以包括栅极电压控制电路，其产生要施加到传输门的栅电极的栅极电压，栅极电压连接在外部输入端子和输入缓冲器的输入端之间，并且传输从外部输入的外部信号 输入端到输入缓冲器的输入端。 栅极电压控制电路作为栅极电压输出基于要作为半导体集成电路的电源电压施加的相对高的第一电压产生的电压，作为栅极电压，作为栅极电压产生电压 基于作为非接入模式中的半导体集成电路的电源电压施加的相对低的第二电压。

    Semiconductor integrated circuit including a circuit protecting against static electricity
    27.
    发明授权
    Semiconductor integrated circuit including a circuit protecting against static electricity 有权
    半导体集成电路包括保护静电的电路

    公开(公告)号：US06703650B2

    公开(公告)日：2004-03-09

    申请号：US09885003

    申请日：2001-06-21

    申请人： Satoshi Ito ,  Hiroshi Seki

    发明人： Satoshi Ito ,  Hiroshi Seki

    IPC分类号： H01L2710

    CPC分类号： H01L27/0255

    摘要： When static electricity having an excessive voltage is applied to a VSS terminal, the static electricity may be transmitted to an inner cell directly connected to a VSS cell before the static electricity is discharged to the outside via an electrostatic protection circuit, possibly resulting in electrostatic destruction. Bypasses are thus provided to bypass the static electricity applied to a VSS terminal to a higher wiring layer, which allow only excessive static electricity to be selectively discharged to the outside via an electrostatic protection circuit.

    摘要翻译： 当施加过电压的静电施加到VSS端子时，静电可以在静电通过静电保护电路向外部排出之前传输到与VSS电池直接连接的内电池，可能导致静电破坏 。 因此提供了旁路，以将施加到VSS端子的静电旁路到较高的布线层，这允许仅通过静电保护电路将过多的静电选择性地放电到外部。