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    Stacked chip process carrier
    21.
    发明授权
    Stacked chip process carrier 失效
    堆叠芯片加工载体

    公开(公告)号：US06279815B1

    公开(公告)日：2001-08-28

    申请号：US09621561

    申请日：2000-07-21

    Applicant: George C. Correia ,  John E. Cronin ,  Edmund J. Sprogis

    Inventor： George C. Correia ,  John E. Cronin ,  Edmund J. Sprogis

    IPC: B23K3102

    CPC classification number: H01L21/6835 ,  B23K37/0408 ,  B23K2101/40 ,  H01L25/50 ,  H01L2221/68313 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2924/30105 ,  Y10T29/53978 ,  H01L2924/00014

    Abstract: The present invention provides an apparatus and methods for holding a first semiconductor device in proper alignment to a second semiconductor device, whose size is different from the first device, while performing a C4 bond between the two devices. The apparatus for holding the two devices in proper alignment consists of a holding fixture, which includes upper and lower pocket receptacles for receiving the semiconductor devices. The semiconductor devices are placed into the respective upper and lower slots aligned to two or more edges of the holding fixture.

    Abstract translation: 本发明提供一种用于在与两个装置之间执行C4键的同时保持第一半导体器件与第一半导体器件的尺寸不同的第二半导体器件的正确对准的装置和方法。 用于将两个装置保持正确对准的装置包括保持夹具，其包括用于接收半导体装置的上部和下部口袋容器。 将半导体器件放置在与保持夹具的两个或更多个边缘对准的相应的上部和下部狭缝中。

    Single twist layout and method for paired line conductors of integrated circuits
    22.
    发明授权
    Single twist layout and method for paired line conductors of integrated circuits 失效
    集成电路成对线导体的单扭曲布局和方法

    公开(公告)号：US5534732A

    公开(公告)日：1996-07-09

    申请号：US567437

    申请日：1995-12-04

    Applicant: John K. DeBrosse ,  Jenifer E. Lary ,  Edmund J. Sprogis

    Inventor： John K. DeBrosse ,  Jenifer E. Lary ,  Edmund J. Sprogis

    IPC: H01L21/822 ,  G11C7/18 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04 ,  H01L27/108 ,  H01L27/10

    CPC classification number: H01L27/108 ,  G11C7/18 ,  H01L23/5225 ,  H01L2924/0002 ,  Y10S257/907

    Abstract: An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.

    Abstract translation: 为主要平行延伸的给定长度的多个成对线导体提供互连阵列布局和方法。 单个交叉区域穿过给定长度中间的成对线导体，其中每对线路导体的线路导体互相交叉，使得对间电容耦合相匹配。 通过将每对线路导体的线路导体分开两个间距并在其间设置不同对线路导线的线路导体来避免对内电容耦合。 应用包括诸如DRAM结构的半导体存储器阵列，以及使用配对的真/互补线导体的地址/数据总线。

    Integrated circuit and design structure having reduced through silicon via-induced stress
    23.
    发明授权
    Integrated circuit and design structure having reduced through silicon via-induced stress 有权
    集成电路和设计结构通过硅通孔引起的应力降低

    公开(公告)号：US09406562B2

    公开(公告)日：2016-08-02

    申请号：US13005883

    申请日：2011-01-13

    Applicant: Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

    Inventor： Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

    IPC: H01L23/48 ,  H01L21/768 ,  G06F17/50

    CPC classification number: H01L21/76898 ,  G06F17/5068 ,  G06F2217/80 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.

    Abstract translation: 本发明的实施例提供了具有减少的通过硅通孔（TSV）的应力和相关IC设计结构和方法的集成电路（IC）。 在一个实施例中，本发明包括设计具有降低的衬底应力的集成电路（IC）的方法，所述方法包括：在IC设计文件中放置多个通过硅通孔（TSV）占位符单元，每个占位符单元具有未定义的 TSV方向 用具有第一取向的第一组TSV单元替换所述多个TSV占位符单元的第一部分; 以及用具有基本上垂直于第一取向的第二取向的第二组TSV单元替换多个TSV占位符单元的第二部分，其中具有第一取向的TSV单元和具有第二取向的TSV单元分散以减少TSV 在IC衬底中引起的应力。

    THROUGH WAFER VIAS WITH DISHING CORRECTION METHODS
    26.
    发明申请
    THROUGH WAFER VIAS WITH DISHING CORRECTION METHODS 有权
    通过具有循环校正方法的WAVER VIAS

    公开(公告)号：US20120137515A1

    公开(公告)日：2012-06-07

    申请号：US13369414

    申请日：2012-02-09

    Applicant: Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    Inventor： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    IPC: H01K3/10

    CPC classification number: H01L21/76898 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.

    Abstract translation: 提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。 在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

    Through wafer vias with dishing correction methods
    27.
    发明授权
    Through wafer vias with dishing correction methods 有权
    通过具有凹陷校正方法的晶片通孔

    公开(公告)号：US08166651B2

    公开(公告)日：2012-05-01

    申请号：US12181359

    申请日：2008-07-29

    Applicant: Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    Inventor： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    IPC: H01K3/10 ,  H05K3/02 ,  H05K3/10 ,  H01L29/40

    CPC classification number: H01L21/76898 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a through wafer via including forming the through wafer via (TWV) into a substrate and through a first dielectric layer over the substrate; planarizing the first dielectric layer using a chemical mechanical polish before forming a second dielectric layer; forming the second dielectric layer over the substrate and the TWV; forming at least one first contact through the second dielectric layer and to the TWV; forming at least one second contact through the second dielectric layer and the first dielectric layer directly and electrically connected to another structure upon the substrate; and forming a first metal wiring layer directly over the second dielectric layer, the first metal wiring layer directly and physically contacting the at least one first contact and the at least one second contact.

    Abstract translation: 一种形成贯穿晶片通孔的方法，包括通过（TWV）形成贯穿晶片进入衬底并穿过衬底上的第一介电层; 在形成第二电介质层之前，使用化学机械抛光平面化第一介电层; 在所述衬底和所述TWV上形成所述第二电介质层; 通过所述第二介电层和所述TWV形成至少一个第一接触; 通过所述第二电介质层和所述第一介电层形成至少一个第二接触，并且在所述衬底上直接电连接到另一结构; 以及直接在所述第二电介质层上方形成第一金属布线层，所述第一金属布线层直接地和物理地接触所述至少一个第一触点和所述至少一个第二触点。

    METHOD OF PRODUCING BONDED WAFER STRUCTURE WITH BURIED OXIDE/NITRIDE LAYERS
    30.
    发明申请
    METHOD OF PRODUCING BONDED WAFER STRUCTURE WITH BURIED OXIDE/NITRIDE LAYERS 审中-公开
    用氧化铝/氮化物层生产粘结的结构的方法

    公开(公告)号：US20110180896A1

    公开(公告)日：2011-07-28

    申请号：US12692983

    申请日：2010-01-25

    Applicant: Gerd Pfeiffer ,  Haizhou Yin ,  Edmund J. Sprogis ,  Subramanian Iyer ,  Zhibin Ren ,  Dae-Gyu Park ,  Oleg Gluschenkov

    Inventor： Gerd Pfeiffer ,  Haizhou Yin ,  Edmund J. Sprogis ,  Subramanian Iyer ,  Zhibin Ren ,  Dae-Gyu Park ,  Oleg Gluschenkov

    IPC: H01L29/06 ,  H01L21/762

    CPC classification number: H01L21/76256

    Abstract: A method of forming a bonded wafer structure includes providing a first semiconductor wafer substrate having a first silicon oxide layer at the top surface of the first semiconductor wafer substrate; providing a second semiconductor wafer substrate; forming a second silicon oxide layer on the second semiconductor wafer substrate; forming a silicon nitride layer on the second silicon oxide layer; and bringing the first silicon oxide layer of the first semiconductor wafer substrate into physical contact with the silicon nitride layer of the second semiconductor wafer substrate to form a bonded interface between the first silicon oxide layer and the silicon nitride layer. Alternatively, a third silicon oxide layer may be formed on the silicon nitride layer before bonding. A bonded interface is then formed between the first and third silicon oxide layers. A bonded wafer structure formed by such a method is also provided.

    Abstract translation: 形成接合晶片结构的方法包括：在第一半导体晶片衬底的顶表面上提供具有第一氧化硅层的第一半导体晶片衬底; 提供第二半导体晶片衬底; 在所述第二半导体晶片衬底上形成第二氧化硅层; 在所述第二氧化硅层上形成氮化硅层; 并且使第一半导体晶片衬底的第一氧化硅层与第二半导体晶片衬底的氮化硅层物理接触以在第一氧化硅层和氮化硅层之间形成键合界面。 或者，可以在接合之前在氮化硅层上形成第三氧化硅层。 然后在第一和第三氧化硅层之间形成键合界面。 还提供了通过这种方法形成的接合晶片结构。

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