公开(公告)号：US10405426B2

公开(公告)日：2019-09-03

申请号：US16169340

申请日：2018-10-24

Applicant: IBIDEN CO., LTD.

Inventor： Takema Adachi ,  Toshihide Makino ,  Hidetoshi Noguchi

IPC: H05K1/11 ,  H05K3/46 ,  H05K1/03 ,  H05K3/06 ,  H05K3/42

Abstract: A printed wiring board includes: a core substrate having a core layer, first and second conductor layers, and through-hole conductors penetrating through the core layer and connecting the conductor layers; and first and second build-up layers each including an insulating layer, an inner side conductor layer, an outermost insulating layer, an outermost conductor layer, and a solder resist layer. Each of the conductor layers includes conductor circuits having substantially a trapezoid cross-sectional shape, and spaces between adjacent conductor circuits, and includes a metal foil, a seed layer, and an electrolytic plating film. The inner side conductor layers have the smallest minimum circuit width, the smallest minimum space width and the largest base angle among the conductor layers. The insulating layers have the smallest ten-point average roughness rz3, rz7 among the ten-point average roughness rz3, rz7, rz1, rz2, rz5 and rz9 of the core layer, insulating layers and outermost insulating layers.

公开(公告)号：US10375828B2

公开(公告)日：2019-08-06

申请号：US16166392

申请日：2018-10-22

Applicant: IBIDEN CO., LTD.

Inventor： Takema Adachi ,  Toshihide Makino ,  Hidetoshi Noguchi

IPC: H05K1/11 ,  H05K1/16 ,  H05K1/02

Abstract: A printed wiring board includes: a core substrate having a core layer and first and second conductor layers; a first build-up layer including a first insulating layer, an inner first conductor layer, an outermost first insulating layer, and an outermost first conductor layer; and a second build-up layer including a second insulating layer, an inner second conductor layer, an outermost second insulating layer, and an outermost second conductor layer. Each conductor layer includes metal foil, seed layer, and electrolytic plating film, t1/T1, t2/T2, u1/U1 and u2/U2 are smaller than 1, and s1/S1 and s2/S2 are larger than 1, where t1, t2, u1, u2, s1 and s2 are electrolytic plating film thicknesses of the first and second and outermost and inner first and second conductor layers, T1, T2, U1, U2, S1 and S2 are metal foil thicknesses of the first and second and outermost and inner first and second conductor layers.

公开(公告)号：US20190200462A1

公开(公告)日：2019-06-27

申请号：US16233210

申请日：2018-12-27

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki Furutani ,  Takema Adachi ,  Toshihide Makino ,  Yasushi Usami

IPC: H05K3/46 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K3/4608 ,  H05K1/115 ,  H05K1/183 ,  H05K3/4655 ,  H05K3/4697

Abstract: A printed wiring board includes a core substrate having cavity to accommodate an electronic component and including a front conductor layer formed on front side of the core substrate, and a back conductor layer formed on back side of the core substrate, through-hole conductors formed through the core substrate such that the through-hole conductors connect the front and back conductor layers of the core substrate, a front build-up layer formed on front surface of the core substrate and including interlayer insulating layers and conductor layers, and a back build-up layer formed on back surface of the core substrate and including interlayer insulating layers and conductor layers. The conductor layers in the front build-up layer include a conductor layer sandwiching one of the interlayer insulating layers with the front conductor layer such that the conductor layer and the front conductor layer have the same electric potential in region surrounding the cavity.

公开(公告)号：US10314168B2

公开(公告)日：2019-06-04

申请号：US16167850

申请日：2018-10-23

Applicant: IBIDEN CO., LTD.

Inventor： Takema Adachi ,  Toshihide Makino ,  Hidetoshi Noguchi

IPC: H05K1/11 ,  H05K3/46 ,  H05K1/02 ,  H05K3/42

Abstract: A printed wiring board includes a core substrate and first and second build-up layers. The substrate includes a core layer, through-hole conductors formed in through holes such that each through hole has first opening tapering from first toward second surface of the core layer, and second opening tapering from second toward first surface of the core layer, and first and second through-hole lands directly connected to the through-hole conductors. Each build-up layer includes an insulating layer, via conductors, via lands, an outermost insulating layer, an outermost conductor layer, and outermost via conductors. Each of the through-hole lands, via lands and outermost conductor layers includes a metal foil, a seed layer and an electrolytic plating film. The foils have mat surfaces such that the mat surfaces of the via lands has ten-point average roughness smaller than ten-point average roughness of the mat surfaces of the through-hole lands and outermost conductor layers.

公开(公告)号：US20160014898A1

公开(公告)日：2016-01-14

申请号：US14798550

申请日：2015-07-14

Applicant: IBIDEN CO., LTD.

Inventor： Takema Adachi ,  Wataru Nakamura ,  Tomoyoshi Hirabayashi

IPC: H05K1/14 ,  H05K1/09 ,  H01L23/498 ,  H05K1/18

CPC classification number: H05K1/144 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H05K1/09 ,  H05K1/185 ,  H05K3/4007 ,  H05K2201/0326 ,  H05K2201/0364 ,  H05K2201/0367 ,  H05K2201/042 ,  H05K2201/09372 ,  H05K2201/10674 ,  H05K2203/054 ,  H05K2203/0723

Abstract: A printed wiring board includes a first circuit substrate having first pads and second pads such that the first pads are positioned to mount an electronic component on the first circuit substrate and that the second pads are positioned to electrically connect the first circuit substrate to a second circuit substrate, and metal posts including plating material and formed on the second pads respectively such that the metal posts are positioned to mount the second circuit substrate on the first circuit substrate. Each of the metal posts has a height h1 and a thickness b such that the metal posts have a value h1/b which is greater than 0.1 and smaller than 1.0 where the value h1/b is obtained by dividing the height h1 by the thickness b.

Abstract translation: 印刷布线板包括具有第一焊盘和第二焊盘的第一电路基板，使得第一焊盘被定位成将电子部件安装在第一电路基板上，并且第二焊盘被定位成将第一电路基板电连接到第二电路 基板和包括电镀材料的金属柱并分别形成在第二焊盘上，使得金属柱被定位成将第二电路基板安装在第一电路基板上。 每个金属柱具有高度h1和厚度b，使得金属柱具有大于0.1且小于1.0的值h1 / b，其中通过将高度h1除以厚度b获得值h1 / b 。

公开(公告)号：US20150255433A1

公开(公告)日：2015-09-10

申请号：US14638324

申请日：2015-03-04

Applicant: IBIDEN CO., LTD.

Inventor： Tomoya DAIZO ,  Takema Adachi ,  Takeshi Furusawa ,  Wataru Nakamura ,  Yuki Ito ,  Yuki Yoshikawa ,  Tomoyoshi Hirabayashi

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A combined substrate includes a first substrate having multiple first metal posts, a second substrate having multiple second metal posts such that the second metal posts are positioned to oppose the first metal posts, respectively, and multiple solder structures interposed between the first metal posts and the second metal posts, respectively. The first metal posts and/or the second metal posts have recessed surfaces formed such that the solder structures are formed on the recessed surfaces, respectively.

Abstract translation: 组合衬底包括具有多个第一金属柱的第一衬底，具有多个第二金属柱的第二衬底，使得第二金属柱分别定位成与第一金属柱相对，以及插入在第一金属柱和第二金属柱之间的多个焊料结构 第二金属柱。 第一金属柱和/或第二金属柱具有形成为使得焊料结构分别形成在凹陷表面上的凹陷表面。

公开(公告)号：US09048229B2

公开(公告)日：2015-06-02

申请号：US14277226

申请日：2014-05-14

Applicant: IBIDEN CO., LTD.

Inventor： Naoto Ishida ,  Takema Adachi

IPC: H01L23/495 ,  H05K1/02 ,  H01L23/498 ,  H05K3/46

CPC classification number: H01L23/49544 ,  H01L23/49811 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/0298 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/068

Abstract: A printed wiring board includes a core substrate, an electronic component accommodated in the substrate, a first buildup layer laminated on first surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the first buildup layer, and a second buildup layer laminated on second surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the second buildup layer. The outermost interlayer resin insulation layer of the first buildup layer has thermal expansion coefficient which is set lower than thermal expansion coefficient of the outermost interlayer resin insulation layer of the second buildup layer.

Abstract translation: 印刷电路板包括芯基板，容纳在基板中的电子部件，层叠在基板的第一表面上的第一累积层，并且包括最外层间树脂绝缘层和最外层导体层，最外层导体层形成在最外层的层间树脂绝缘层上 第一累积层和层叠在基板的第二表面上的第二堆积层，并且包括形成在第二堆积层的最外层间树脂绝缘层上的最外层间树脂绝缘层和最外导电层。 第一堆积层的最外层间树脂绝缘层的热膨胀系数设定为低于第二堆积层的最外层间树脂绝缘层的热膨胀系数。

公开(公告)号：US08742553B2

公开(公告)日：2014-06-03

申请号：US13690570

申请日：2012-11-30

Applicant: Ibiden Co., Ltd.

Inventor： Naoto Ishida ,  Takema Adachi

IPC: H01L23/495

CPC classification number: H01L23/49544 ,  H01L23/49811 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/0298 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/068

Abstract: A printed wiring board includes a core substrate, a first buildup layer laminated on a first surface of the core substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the first buildup layer, and a second buildup layer laminated on a second surface of the core substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the second buildup layer. The outermost conductive layer of the first buildup layer includes pads positioned to mount a semiconductor device on a surface of the first buildup layer, and the outermost interlayer resin insulation layer of the first buildup layer has a thermal expansion coefficient which is set lower than a thermal expansion coefficient of the outermost interlayer resin insulation layer of the second buildup layer.

Abstract translation: 印刷电路板包括芯基板，层叠在芯基板的第一表面上并且包括最外层间树脂绝缘层的第一累积层和形成在第一堆积层的最外层间树脂绝缘层上的最外导电层，以及 层叠在所述芯基板的第二表面上并且包括最外层间树脂绝缘层和形成在所述第二堆积层的最外层间树脂绝缘层上的最外导体层的第二堆积层。 第一累积层的最外面的导电层包括定位成将半导体器件安装在第一堆积层的表面上的焊盘，第一堆积层的最外层间树脂绝缘层的热膨胀系数设定为低于热 第二堆积层的最外层间树脂绝缘层的膨胀系数。

公开(公告)号：US11882656B2

公开(公告)日：2024-01-23

申请号：US17708486

申请日：2022-03-30

Applicant: IBIDEN CO., LTD.

Inventor： Takema Adachi ,  Daisuke Minoura

IPC: H05K1/11 ,  H05K3/38 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K1/113 ,  H05K3/383 ,  H05K3/389 ,  H05K3/0035 ,  H05K3/428 ,  H05K2201/096 ,  H05K2201/09454 ,  H05K2201/09827 ,  H05K2203/072 ,  H05K2203/0723

Abstract: A wiring substrate includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on the insulating layer, a connection conductor penetrating through the insulating layer and connecting the first and second conductor layers, and a coating film formed on a surface of the first conductor layer and adhering the first conductor layer and the insulating layer. The first conductor layer includes a conductor pad in contact with the connection conductor such that the conductor pad has a surface having a first region and a second region on second conductor layer side and that surface roughness of the first region is different from surface roughness of the second region, and the conductor pad of the first conductor layer is formed such that the first region is covered by the coating film and that the second region is covered by the connection conductor.

公开(公告)号：US10368440B2

公开(公告)日：2019-07-30

申请号：US16165743

申请日：2018-10-19

Applicant: IBIDEN CO., LTD.

Inventor： Takema Adachi ,  Toshihide Makino ,  Hidetoshi Noguchi

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

Abstract: A printed wiring board includes: a core substrate having a core layer, conductor layers on the core layer, and through-hole conductors; a first build-up layer including an insulating layer on the substrate, an inner side conductor layer on the insulating layer, an outermost insulating layer on the inner side conductor layer, and an outermost conductor layer on the outermost insulating layer; and a second build-up layer including an insulating layer on the substrate, an inner side conductor layer on the insulating layer, an outermost insulating layer on the inner side conductor layer, and an outermost conductor layer on the outermost insulating layer. Each of the conductor layers, inner side conductor layers, and outermost conductor layers has a metal foil, a seed layer and an electrolytic plating film, and that each inner side conductor layer has the smallest thickness among the conductor layers, inner side conductor layers and outermost conductor layers.