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    Method of porosifying part of a semiconductor wafer
    21.
    发明授权
    Method of porosifying part of a semiconductor wafer 有权

    公开(公告)号：US11810779B2

    公开(公告)日：2023-11-07

    申请号：US17841781

    申请日：2022-06-16

    Applicant: Infineon Technologies AG

    Inventor： Sophia Friedler ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri

    IPC: H01L21/02 ,  H01L21/465 ,  H01L21/8258

    CPC classification number: H01L21/0203 ,  H01L21/02019 ,  H01L21/465 ,  H01L21/8258

    Abstract: A method includes: in a semiconductor wafer having a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a front surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer, wherein forming the porous region comprises bringing in contact a porosifying agent with the front surface of the first semiconductor layer and applying a voltage between the first semiconductor layer and a first electrode that is in contact with the porosifying agent, wherein applying the voltage comprises applying the voltage between the first electrode and an edge region of the first semiconductor layer.

    Metallization layers for semiconductor devices and methods of forming thereof
    24.
    发明授权
    Metallization layers for semiconductor devices and methods of forming thereof 有权

    公开(公告)号：US10439062B2

    公开(公告)日：2019-10-08

    申请号：US15261566

    申请日：2016-09-09

    Applicant: Infineon Technologies AG

    Inventor： Bernhard Goller ,  Kurt Matoy

    IPC: H01L29/78 ,  H01L21/306 ,  H01L21/308 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/34 ,  H01L29/40 ,  H01L29/861 ,  H01L21/74

    Abstract: A method of fabricating a semiconductor device includes etching a first surface of a semiconductor substrate from a first side using a first etching process to expose a second surface. The second surface includes a first plurality of features. The first plurality of features has an average height that is a first height. The second surface of the semiconductor substrate is etched from the first side using a second etching process to expose a third surface of the semiconductor substrate. The second etching process converts the first plurality of features into a second plurality of features. The second plurality of features has an average height that is a second height. The second height is less than the first height. A conductive layer is formed over the third surface of the semiconductor substrate using a physical deposition process.

    Semiconductor Chip Including Self-Aligned, Back-Side Conductive Layer and Method for Making the Same
    25.
    发明申请
    Semiconductor Chip Including Self-Aligned, Back-Side Conductive Layer and Method for Making the Same 审中-公开

    公开(公告)号：US20190096758A1

    公开(公告)日：2019-03-28

    申请号：US16144169

    申请日：2018-09-27

    Applicant: Infineon Technologies AG

    Inventor： Ingo Muri ,  Bernhard Goller

    IPC: H01L21/768 ,  H01L23/528 ,  H01L21/302 ,  H01L21/321 ,  H01L21/78

    Abstract: A method for manufacturing a semiconductor device includes: partially dicing a substrate wafer arrangement having a plurality of semiconductor chips, wherein the partial dicing forms trenches around the semiconductor chips on a front-side of the substrate wafer arrangement, the depth being greater than a target thickness of a semiconductor chip; filling the trenches with a polymer material to form a polymer structure; first thinning of the back-side to expose portions of the polymer structure; forming a conductive layer on the back-side of the substrate wafer arrangement so that the exposed portions of the polymer structure are covered; second thinning of the back-side to form insular islands of conductive material, the insular islands separated from each other by the polymer structure, each insular island corresponding to a respective one of the semiconductor chips; and dicing the substrate wafer arrangement along the polymer structure.

    Systems and methods for non-volatile memory
    29.
    发明授权
    Systems and methods for non-volatile memory 有权
    用于非易失性存储器的系统和方法

    公开(公告)号：US09064557B2

    公开(公告)日：2015-06-23

    申请号：US14085991

    申请日：2013-11-21

    Applicant: Infineon Technologies AG

    Inventor： Wolfgang Scherr ,  Michael Sorger ,  Guenther Wellenzohn ,  Magdalena Forster ,  Philemon Schweizer ,  Katharina Schmut ,  Bernhard Goller ,  Mario Motz

    IPC: G11C7/00 ,  G11C5/14

    CPC classification number: G11C5/141

    Abstract: A self powered memory system is disclosed. The system includes a volatile supply component, a battery component, a switch component, and a volatile memory component. The volatile supply component is configured to provide a time varying supply. The battery component is configured to generate a non-volatile supply. The switch component is configured to generate a persistent supply from the time varying supply and the non-volatile supply. The volatile memory component is configured to maintain data by using the persistent supply.

    Abstract translation: 公开了一种自供电的存储器系统。 该系统包括易失性电源组件，电池组件，开关组件和易失性存储器组件。 易失性供应部件配置成提供时变电源。 电池组件配置成产生非易失性电源。 开关组件被配置为从时变电源和非易失性电源产生持续电源。 易失性存储器组件被配置为通过使用持续电源来维护数据。

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