公开(公告)号：US09793182B2

公开(公告)日：2017-10-17

申请号：US14484928

申请日：2014-09-12

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez

IPC: H01L23/544 ,  H01L21/66 ,  H01L23/522 ,  H01L21/78 ,  H01L29/34 ,  H01L29/36 ,  H01L21/302 ,  H01L21/265 ,  H01L21/306

CPC classification number: H01L22/20 ,  H01L21/26513 ,  H01L21/302 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/78 ,  H01L22/12 ,  H01L23/522 ,  H01L29/34 ,  H01L29/36 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device arrangement includes a semiconductor substrate which includes a semiconductor substrate front side and a semiconductor substrate back side. The semiconductor substrate includes at least one electrical element formed at the semiconductor substrate front side. The semiconductor device arrangement further includes at least one porous semiconductor region formed at the semiconductor substrate back side.

公开(公告)号：US09728395B2

公开(公告)日：2017-08-08

申请号：US14867839

申请日：2015-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Helmut Oefner ,  Nico Caspary ,  Mohammad Momeni ,  Reinhard Ploss ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze

IPC: H01L21/02 ,  H01L21/268 ,  H01L21/324 ,  H01L29/66 ,  H01L21/18 ,  H01L21/225 ,  H01L21/28 ,  H01L21/322

CPC classification number: H01L29/7393 ,  H01L21/02002 ,  H01L21/02005 ,  H01L21/02008 ,  H01L21/0201 ,  H01L21/02016 ,  H01L21/187 ,  H01L21/2257 ,  H01L21/268 ,  H01L21/28238 ,  H01L21/3221 ,  H01L21/3225 ,  H01L21/324 ,  H01L21/3242 ,  H01L21/76256 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66325 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

Abstract: A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.

公开(公告)号：US20170194450A1

公开(公告)日：2017-07-06

申请号：US15465688

申请日：2017-03-22

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Andreas Haertl ,  Francisco Javier Santos Rodriguez ,  André Rainer Stegner ,  Daniel Schloegl

IPC: H01L29/47 ,  H01L21/285

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization material over a semiconductor body; performing a heating process so as to form at least one region in the semiconductor body including a eutectic of the first metallization material and material of the semiconductor body; and depositing a second metallization material over the semiconductor body so as to contact the semiconductor body via the at least one region in the semiconductor body.

公开(公告)号：US20170033011A1

公开(公告)日：2017-02-02

申请号：US15224099

申请日：2016-07-29

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Wolfgang Lehnert ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze

IPC: H01L21/78 ,  H01L29/16 ,  H01L29/20 ,  H01L21/66

CPC classification number: H01L21/7813 ,  H01L21/02002 ,  H01L21/76251 ,  H01L21/78 ,  H01L22/14 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/8611 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A method of forming a semiconductor device and a semiconductor device are provided. The method includes providing a wafer stack including a carrier wafer comprising graphite and a device wafer comprising a wide band-gap semiconductor material and having a first side and a second side opposite the first side, the second side being attached to the carrier wafer, defining device regions of the wafer stack, partly removing the carrier wafer so that openings are formed in the carrier wafer arranged within respective device regions and that the device wafer is supported by a residual of the carrier wafer; and further processing the device wafer while the device wafer remains supported by the residual of the carrier wafer.

Abstract translation: 提供一种形成半导体器件和半导体器件的方法。 该方法包括提供包括包括石墨的载体晶片和包括宽带隙半导体材料并且具有与第一侧相对的第一侧和第二侧的器件晶片的晶片堆叠，第二侧附接到载体晶片，限定 晶片堆叠的器件区域，部分地去除载体晶片，使得在布置在各个器件区域内的载体晶片中形成开口，并且器件晶片由载体晶片的残余物支撑; 并且在器件晶片保持由载体晶片的剩余部分支撑的同时进一步处理器件晶片。

公开(公告)号：US09443971B2

公开(公告)日：2016-09-13

申请号：US14940797

申请日：2015-11-13

Applicant: Infineon Technologies AG

Inventor： Andreas Haertl ,  Frank Hille ,  Francisco Javier Santos Rodriguez ,  Daniel Schloegl ,  Andre Rainer Stegner ,  Christoph Weiss

IPC: H01L29/00 ,  H01L21/22 ,  H01L21/38 ,  H01L29/78 ,  H01L29/739 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/063 ,  H01L21/26506 ,  H01L21/28568 ,  H01L29/0607 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/32 ,  H01L29/36 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66136 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66674 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/861

Abstract: A semiconductor device includes a diffusion barrier layer, a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers. The first semiconductor region includes a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers, a contact region in contact with the diffusion barrier layer, the contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration, and a damage region between the contact region and the transition region. The damage region is configured for reducing the lifetime and/or the mobility of the first charge carriers of the damage region as compared to the lifetime and/or the mobility of the first charge carriers of the contact region and the transition region.

Abstract translation: 半导体器件包括扩散阻挡层，具有第一导电类型的第一电荷载流子的第一半导体区域和具有第二电荷载流子的第二半导体区域。 第一半导体区域包括与第二半导体区域接触的过渡区域，过渡区域具有第一电荷载流子的第一浓度，与扩散阻挡层接触的接触区域，接触区域具有第一浓度的第一 电荷载体，其中第二浓度高于第一浓度，以及在接触区域和过渡区域之间的损伤区域。 损伤区域被配置为与接触区域和过渡区域的第一电荷载流子的寿命和/或迁移率相比，减小损伤区域的第一电荷载流子的寿命和/或迁移率。

公开(公告)号：US20160104622A1

公开(公告)日：2016-04-14

申请号：US14867839

申请日：2015-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Helmut Oefner ,  Nico Caspary ,  Mohammad Momeni ,  Reinhard Ploss ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze

IPC: H01L21/28 ,  H01L21/322

CPC classification number: H01L29/7393 ,  H01L21/02002 ,  H01L21/02005 ,  H01L21/02008 ,  H01L21/0201 ,  H01L21/02016 ,  H01L21/187 ,  H01L21/2257 ,  H01L21/268 ,  H01L21/28238 ,  H01L21/3221 ,  H01L21/3225 ,  H01L21/324 ,  H01L21/3242 ,  H01L21/76256 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66325 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

Abstract: A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.

Abstract translation: 一种用于制造衬底晶片100的方法包括提供具有第一侧面（111）和第二侧面（112）的器件晶片（110）; 至少在第二侧（112）的区域（112a）中对器件晶片（110）进行第一高温工艺以减少器件晶片（110）的氧含量; 将器件晶片（110）的第二侧（112）接合到载体晶片（120）的第一侧（121）以形成衬底晶片（100）; 处理衬底晶片（100）的第一侧（101）以减小器件晶片（110）的厚度; 对所述衬底晶片（100）进行第二高温处理以至少减少所述器件晶片（110）的氧含量; 以及在所述第二高温处理之后至少部分地将至少一个半导体部件（140）集成到所述器件晶片（110）中。

公开(公告)号：US09287165B2

公开(公告)日：2016-03-15

申请号：US13927923

申请日：2013-06-26

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Matthias Müller ,  Francisco Javier Santos Rodriguez ,  Daniel Schlögl

IPC: H01L21/76 ,  H01L21/768 ,  H01L29/06

CPC classification number: H01L21/76841 ,  H01L29/0615 ,  H01L29/0619

Abstract: A power semiconductor device includes a semiconductor body, having an active zone and a high voltage peripheral zone laterally adjacent to each other, the high voltage peripheral zone laterally surrounding the active zone. The device further includes a metallization layer on a front surface of the semiconductor body and connected to the active zone, a first barrier layer, comprising a high-melting metal or a high-melting alloy, between the active zone and the metallization layer, and a second barrier layer covering at least a part of the peripheral zone, the second barrier layer comprising an amorphous semi-isolating material. The first barrier layer and the second barrier layer partially overlap and form an overlap zone. The overlap zone extends over an entire circumference of the active zone. A method for producing such a power semiconductor device is also provided.

Abstract translation: 功率半导体器件包括具有横向相邻的有源区和高电压周边区的半导体本体，所述高电压周边区横向围绕有源区。 该器件还包括在半导体主体的前表面上并连接到有源区的金属化层，在活性区和金属化层之间包含高熔点金属或高熔点合金的第一阻挡层，以及 覆盖所述周边区域的至少一部分的第二阻挡层，所述第二阻挡层包括非晶半隔离材料。 第一阻挡层和第二阻挡层部分地重叠并形成重叠区域。 重叠区域在活动区域​​的整个圆周上延伸。 还提供了一种用于制造这种功率半导体器件的方法。

公开(公告)号：US20140151789A1

公开(公告)日：2014-06-05

申请号：US13690328

申请日：2012-11-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Maria Cotorogea ,  Hans Peter Felsl ,  Yvonne Gawlina ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze ,  Georg Seibert ,  Andre Rainer Stegner ,  Wolfgang Wagner

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.

Abstract translation: 半导体器件包括在第一沟槽中包括第一栅电极的第一晶体管单元。 半导体器件还包括在第二沟槽中包括第二栅电极的第二晶体管单元，其中第一和第二栅极电连接。 半导体器件还包括在第一和第二沟槽之间的第三沟槽，其中第三沟槽从半导体本体的第一侧比第一和第二沟槽更深地延伸到半导体本体中。 半导体器件还包括覆盖第三沟槽的底侧和第三沟槽壁的第三沟槽中的电介质。

公开(公告)号：US12272738B2

公开(公告)日：2025-04-08

申请号：US18351600

申请日：2023-07-13

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Roland Rupp ,  Francisco Javier Santos Rodriguez

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L21/683 ,  H01L21/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/739 ,  H01L29/78

Abstract: A method includes: providing a layer of porous silicon carbide supported by a silicon carbide substrate; providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide; forming semiconductor devices in the layer of epitaxial silicon carbide; and separating the silicon carbide substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. The layer of porous silicon carbide includes dopants defining a resistivity of the layer of porous silicon carbide. The resistivity of the layer of porous silicon carbide is different from a resistivity of the silicon carbide substrate. Additional methods are described.

公开(公告)号：US11735642B2

公开(公告)日：2023-08-22

申请号：US17314672

申请日：2021-05-07

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Roland Rupp ,  Francisco Javier Santos Rodriguez

IPC: H01L29/16 ,  H01L29/66 ,  H01L21/02 ,  H01L21/683 ,  H01L21/04 ,  H01L21/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/66068 ,  H01L21/0262 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/02658 ,  H01L21/048 ,  H01L21/0475 ,  H01L21/6835 ,  H01L21/78 ,  H01L21/7806 ,  H01L21/7813 ,  H01L29/0804 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66053 ,  H01L29/7395 ,  H01L29/7802

Abstract: A method includes providing a layer of porous silicon carbide supported by a silicon carbide substrate, providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide, forming a plurality of semiconductor devices in the layer of epitaxial silicon carbide, and separating the substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. Additional methods are described.