公开(公告)号：US20170358494A1

公开(公告)日：2017-12-14

申请号：US15182387

申请日：2016-06-14

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Manfred Engelhardt ,  Gudrun Stranzl

IPC: H01L21/78 ,  H01L21/3065 ,  H01J37/32 ,  H01L29/16 ,  H01L23/495 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01J37/32009 ,  H01J37/32091 ,  H01J37/3244 ,  H01J37/32724 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L29/1608 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method of forming a semiconductor device includes forming an active region in a first side of a silicon carbide substrate, the silicon carbide substrate having a second side opposite the first side and forming a contact pad at the first side. The contact pad is coupled to the active region. The method further includes forming an etch stop layer over the contact pad and plasma dicing the silicon carbide substrate from the second side. The plasma dicing etches through the silicon carbide substrate and stops on the etch stop layer. The diced silicon carbide substrate is held together by the etch stop layer. The diced silicon carbide substrate is attached on a carrier. The diced silicon carbide substrate is separated into silicon carbide dies by cleaving the etch stop layer.

公开(公告)号：US20170076970A1

公开(公告)日：2017-03-16

申请号：US15359620

申请日：2016-11-23

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Rainer Leuschner ,  Bernhard Goller ,  Bernhard Boche ,  Manfred Engelhardt ,  Hermann Wendt ,  Bernd Noehammer ,  Karl Mayer ,  Michael Roesner ,  Monika Cornelia Voerckel

IPC: H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L21/285 ,  H01L21/304 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/6835 ,  H01L21/0331 ,  H01L21/283 ,  H01L21/2855 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/6836 ,  H01L21/76895 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/0001

Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

Abstract translation: 用于处理半导体工件的方法可以包括提供包括一个或多个切口区域的半导体工件; 通过从所述工件的第一侧移除来自所述一个或多个切割区域的材料，在所述工件中形成一个或多个沟槽; 将具有第一侧的工件安装到载体上; 从工件的第二侧使工件变薄; 以及在所述工件的第二侧上形成金属化层。

公开(公告)号：US09490103B2

公开(公告)日：2016-11-08

申请号：US14977625

申请日：2015-12-21

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Gudrun Stranzl ,  Markus Zundel ,  Hubert Maier

IPC: H01L21/683 ,  H01L21/78 ,  H01J37/32 ,  B28D5/00

CPC classification number: H01J37/32009 ,  B28D5/00 ,  H01J2237/334 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834

Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.

公开(公告)号：US09455192B2

公开(公告)日：2016-09-27

申请号：US14226666

申请日：2014-03-26

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Manfred Engelhardt ,  Johann Schmid ,  Gudrun Stranzl ,  Joachim Hirschler

IPC: H01L21/46 ,  H01L21/78 ,  H01L21/768 ,  H01L23/00 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/7806 ,  H01L21/02057 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2924/10157 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes attaching a substrate to a carrier using an adhesive component and forming a through trench through the substrate to expose the adhesive component. At least a portion of the adhesive component is etched and a metal layer is formed over sidewalls of the through trench.

Abstract translation: 根据本发明的实施例，一种形成半导体器件的方法包括：使用粘合剂组件将衬底附着到载体上，并通过衬底形成通孔以暴露粘合剂组分。 蚀刻粘合剂组分的至少一部分，并且在通孔的侧壁上形成金属层。

公开(公告)号：US09449928B2

公开(公告)日：2016-09-20

申请号：US14252804

申请日：2014-04-15

Applicant: Infineon Technologies AG

Inventor： Joachim Hirschler ,  Gudrun Stranzl

IPC: H01L21/302 ,  H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/768 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L23/564 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A layer arrangement in accordance with various embodiments may include: a wafer; a passivation disposed over the wafer; a protection layer disposed over at least a surface of the passivation facing away from the wafer; and a mask layer disposed over at least a surface of the protection layer facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation, and wherein the mask layer includes a material that is selectively etchable to the material of the protection layer.

Abstract translation: 根据各种实施例的层布置可以包括：晶片; 设置在晶片上的钝化层; 保护层，设置在远离晶片的钝化面的至少一个表面上; 以及掩模层，其设置在所述保护层的远离所述晶片的至少一个表面上，其中所述保护层包括可选择性地蚀刻到所述钝化材料的材料，并且其中所述掩模层包括可选择性地蚀刻的材料 到保护层的材料。

公开(公告)号：US20140357055A1

公开(公告)日：2014-12-04

申请号：US13903013

申请日：2013-05-28

Applicant: Infineon Technologies AG

Inventor： Anja Gissibl ,  Hermann Wendt ,  Thomas Fischer ,  Bernhard Weidgans ,  Gudrun Stranzl ,  Tobias Schmidt ,  Dietrich Bonart

IPC: H01L21/306 ,  H01L21/78 ,  H01L21/3065

CPC classification number: H01L21/78 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76841 ,  H01L21/76892

Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.

Abstract translation: 提供了一种用于处理半导体工件的方法，其可以包括：提供包括设置在半导体工件侧面的金属化层堆叠的半导体工件，金属化层堆叠包括至少第一层和设置在第一层上的第二层 层，其中所述第一层包含第一材料，并且所述第二层包含不同于所述第一材料的第二材料; 图案化金属化层堆叠，其中图案化金属化层堆叠包括通过蚀刻溶液湿法蚀刻第一层和第二层，蚀刻溶液对于第一材料和第二材料具有至少基本上相同的蚀刻速率。

公开(公告)号：US11077525B2

公开(公告)日：2021-08-03

申请号：US16374265

申请日：2019-04-03

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Markus Menath ,  Gudrun Stranzl

IPC: B23K26/362 ,  B23K26/40 ,  H01L29/16 ,  H01L21/3065 ,  H01L21/67

Abstract: A method of processing silicon carbide containing crystalline substrate is provided. The method includes pyrolyzing a surface of the silicon carbide containing crystalline substrate to produce a silicon and carbon containing debris layer over the silicon carbide containing crystalline substrate, and removing the silicon and carbon containing debris layer, wherein the pyrolyzing and the removing is repeated at least once.

公开(公告)号：US10672716B2

公开(公告)日：2020-06-02

申请号：US16029934

申请日：2018-07-09

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl ,  Manfred Engelhardt ,  Martin Zgaga

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/3065

Abstract: An integrated circuit substrate and a method for manufacturing the same are disclosed. In an embodiment a method includes providing a wafer having a plurality of active areas, each active area being provided in a separate die area and for each active area, providing a code pattern outside the active area, the code pattern being associated with the die area.

公开(公告)号：US10032670B2

公开(公告)日：2018-07-24

申请号：US15182387

申请日：2016-06-14

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Manfred Engelhardt ,  Gudrun Stranzl

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/67 ,  H01L29/16 ,  H01L23/495 ,  H01J37/32

Abstract: A method of forming a semiconductor device includes forming an active region in a first side of a silicon carbide substrate, the silicon carbide substrate having a second side opposite the first side and forming a contact pad at the first side. The contact pad is coupled to the active region. The method further includes forming an etch stop layer over the contact pad and plasma dicing the silicon carbide substrate from the second side. The plasma dicing etches through the silicon carbide substrate and stops on the etch stop layer. The diced silicon carbide substrate is held together by the etch stop layer. The diced silicon carbide substrate is attached on a carrier. The diced silicon carbide substrate is separated into silicon carbide dies by cleaving the etch stop layer.

公开(公告)号：US09966277B2

公开(公告)日：2018-05-08

申请号：US15361108

申请日：2016-11-25

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/498 ,  H01L27/02 ,  H01L23/31 ,  H01L29/861

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.