公开(公告)号：US10832766B2

公开(公告)日：2020-11-10

申请号：US16146814

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Pranav Kalavade ,  Uday Chandrasekhar ,  Trupti Bemalkhedkar ,  Chang Wan Ha

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

Abstract: An apparatus and/or system is described including a memory device or a controller to perform programming and verification operations including application of a shared voltage level to verify two program voltage levels of a multi-level cell device. For example, in embodiments, the control circuitry performs a program operation to program a memory cell and performs a verification operation by applying a single or shared verify voltage level to verify that the memory cell is programmed to a corresponding program voltage level. In embodiments, the program voltage level is one of two consecutive program voltage levels of a plurality of program voltage levels to be verified by application of the shared verify voltage. Other embodiments are disclosed and claimed.

公开(公告)号：US20190043567A1

公开(公告)日：2019-02-07

申请号：US16115372

申请日：2018-08-28

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Shantanu Rajwade ,  Rohit Shenoy ,  Aliasgar Madraswala ,  Pranav Kalavade

IPC: G11C11/56 ,  G11C16/26 ,  H01L23/00 ,  G06F3/06

Abstract: An apparatus and/or system is described including a memory device or a controller for a memory device to perform an adjustment of a read operation time for data stored in the memory device. In embodiments, the apparatus may receive a request for data stored in the memory device and a read operation time adjustment module operable by the controller may acquire a first operation temperature of the memory device, obtained at a time of programming of the data stored in the memory device. The apparatus may acquire a second operation temperature of the memory device, obtained after the request for the data stored in the memory device is received. Based at least partially on the first operation temperature and the second operation temperature, the apparatus may adjust the read operation time to read the data. Other embodiments are disclosed and claimed.

公开(公告)号：US10109361B1

公开(公告)日：2018-10-23

申请号：US15637481

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Pranav Kalavade ,  Rohit S. Shenoy ,  Aliasgar S. Madraswala ,  Donia Sebastian ,  Xin Guo

IPC: G11C16/04 ,  G11C16/34

Abstract: A memory programmer apparatus may include a first-level programmer to program a first-level cell portion of a multi-level memory in a first pass, a coarse programmer to coarse program a second-level cell portion of the multi-level memory in the first pass, wherein the second-level cell portion includes more levels than the first-level cell portion, and a fine programmer to fine program the second-level cell portion of the multi-level memory in a second pass from data programmed in the first-level cell portion in the first pass.

公开(公告)号：US20170371779A1

公开(公告)日：2017-12-28

申请号：US15195328

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Andrea D'alessandro ,  Pranav Kalavade ,  Violante Moschiano

IPC: G06F12/02 ,  G11C16/04 ,  G06F11/07 ,  G11C16/26 ,  G11C16/10

CPC classification number: G06F12/0246 ,  G06F11/073 ,  G06F11/076 ,  G06F2212/2022 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  G11C2211/5644

Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a write request from a computing host, the write request to specify data to be written to the NAND flash memory; perform a number of program loops to program the data into a plurality of cells of the NAND flash memory, wherein a program loop comprises application of a program voltage to a wordline of the memory to change the threshold voltage of at least one cell of the plurality of cells; and wherein the number of program loops is to be determined prior to receipt of the write request and based on a distribution of threshold voltages of the cells or determined based on tracking a number of program errors for only a portion of the plurality of cells.

公开(公告)号：US09740419B2

公开(公告)日：2017-08-22

申请号：US15419563

申请日：2017-01-30

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Aliasgar Madraswala ,  Pranav Kalavade ,  Xin Guo ,  David Pelster ,  Myron Loewen ,  Feng Zhu ,  Brennan A. Watt

IPC: G11C11/34 ,  G06F3/06 ,  G06F12/0811

CPC classification number: G06F3/0625 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0688 ,  G06F12/0811 ,  G06F2212/283 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/225 ,  G11C2211/5641

Abstract: Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes setting an alternate data cache (PDC1) to a logical AND of a secondary data cache (SDC) and a primary data cache (PDC0). The PDC1 is set to a logical AND of the PDC1 and a first result of a first sense operation. The PDC0 is set to a logical AND of the PDC0 and an inverse value of the PDC1. The PDC1 is set to a logical AND of the SDC and the PDC0. The PDC1 is set to a logical AND of the PDC1 and an inverse value of a second result of a second sense operation. The SDC is set to a logical AND of the SDC and the PDC0. The SDC is set to a logical OR of the SDC or the PDC0. The PDC0 is set to a logical AND of the PDC0 and a third result of a third sensing operation.

公开(公告)号：US20170123946A1

公开(公告)日：2017-05-04

申请号：US14932870

申请日：2015-11-04

Applicant: Intel Corporation

Inventor： Ning Wu ,  Xin Guo ,  Ramkarthik Ganesan ,  Pranav Kalavade ,  Robert Frickey

IPC: G06F11/20

CPC classification number: G06F11/2094 ,  G06F11/141 ,  G06F11/1441 ,  G06F12/0238 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2201/805 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/214 ,  G06F2212/222 ,  G06F2212/7203 ,  G06F2212/7204 ,  G06F2212/7211 ,  G11C2211/5641

Abstract: Technology for an apparatus is described. The apparatus can include a first non-volatile memory, a second non-volatile memory to have a write access time faster than the first non-volatile memory, and a memory controller. The memory controller can be configured to detect corrupted data in a selected data region in the first non-volatile memory. The selected data region can be associated with an increased risk of data corruption after data is written from the second non-volatile memory to the first non-volatile memory. Uncorrupted data in the second non-volatile memory that corresponds to the corrupted data in the first non-volatile memory can be identified. Data recovery in the first non-volatile memory can be performed by replacing the corrupted data in the first non-volatile memory with uncorrupted data from the second non-volatile memory.

公开(公告)号：US20170117049A1

公开(公告)日：2017-04-27

申请号：US14922611

申请日：2015-10-26

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Akira Goda ,  Pranav Kalavade ,  Krishna K. Parat ,  Hiroyuki Sanda

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0441 ,  G11C16/0458 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3427 ,  G11C16/3477

Abstract: Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devices associated with the target sub-block. Additionally, the leakage current condition may be inhibited in one or more remaining SGD devices associated with remaining sub-blocks of NAND strings in the memory. In one example, triggering the leakage current condition in the one or more target SGD devices includes setting a gate voltage of the one or more target SGD devices to a value that generates a reverse voltage that exceeds a threshold corresponding to the leakage current condition.

公开(公告)号：US20160336073A1

公开(公告)日：2016-11-17

申请号：US15050871

申请日：2016-02-23

Applicant: Intel Corporation

Inventor： Krishna K. Parat ,  Pranav Kalavade ,  Koichi Kawai ,  Akira Goda

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C8/12 ,  G11C16/04 ,  G11C16/3409 ,  G11C16/3445

Abstract: Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify

Abstract translation: 擦除和/或软件编程NAND存储器块的方法和装置可以包括在包括两个或多个子块的NAND存储器块上执行擦除周期，验证两个或更多个子块直到子块失败 验证，停止验证以响应失败的验证，在NAND存储器块上执行另一个擦除周期，并重新启动以验证子块处的两个或更多个子块，验证失败

公开(公告)号：US09418000B2

公开(公告)日：2016-08-16

申请号：US14579971

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Shyam Sunder Raghunathan ,  Iwen Chao ,  Xin Guo ,  Pranav Kalavade ,  Krishna K. Parat ,  Feng Zhu

IPC: G11C16/04 ,  G06F12/02 ,  G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/32 ,  G06F11/10 ,  G11C16/10

CPC classification number: G06F12/0246 ,  G06F11/1084 ,  G06F2212/7211 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/32 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028

Abstract: Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory. Other examples are also disclosed and claimed.

Abstract translation: 描述了在非易失性存储器件中实现动态存储器管理的装置，系统和方法。 在一个示例中，控制器包括用于监视非易失性存储器的至少一个性能参数的逻辑，确定何时至少一个性能参数通过指示非易失性存储器性能下降的阈值，以及响应于该至少一个 性能参数通过阈值，以修改非易失性存储器的至少一个操作属性。 还公开并要求保护其他实例。

公开(公告)号：US09305654B2

公开(公告)日：2016-04-05

申请号：US13719558

申请日：2012-12-19

Applicant: Intel Corporation

Inventor： Krishna K. Parat ,  Pranav Kalavade ,  Koichi Kawai ,  Akira Goda

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/16 ,  G11C8/12 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C8/12 ,  G11C16/04 ,  G11C16/3409 ,  G11C16/3445

Abstract: Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify.

Abstract translation: 擦除和/或软件编程NAND存储器块的方法和装置可以包括在包括两个或多个子块的NAND存储器块上执行擦除周期，验证两个或更多个子块直到子块失败 验证，停止验证以响应失败的验证，在NAND存储器块上执行另一个擦除周期，并重新启动以验证子块处的两个或更多个子块，验证失败。