公开(公告)号：US09674945B2

公开(公告)日：2017-06-06

申请号：US13624288

申请日：2012-09-21

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Kevin Lin ,  Feras Eid ,  Qing Ma

IPC: H01L23/34 ,  H05K1/02 ,  H01L25/00 ,  H05K1/18 ,  H05K3/00

CPC classification number: H05K1/0272 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/1815 ,  H01L2924/18162 ,  H05K1/0212 ,  H05K1/185 ,  H05K3/0097 ,  H05K2201/097 ,  H05K2203/1536 ,  H05K2203/308 ,  Y10T29/4913

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a microfluidic die to a package structure, wherein the microfluidic die comprises a plurality of asymmetric electrodes that may be coupled with signal pads disposed within the package structure.

公开(公告)号：US09673131B2

公开(公告)日：2017-06-06

申请号：US13859659

申请日：2013-04-09

Applicant: Intel Corporation

Inventor： Chuan Hu ,  Qing Ma ,  Chia-Pin Chiu

IPC: H01L23/52 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49894 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for integrated circuit package assemblies including a glass solder mask layer and/or bridge. In one embodiment, an apparatus includes one or more build-up layers having electrical routing features and a solder mask layer composed of a glass material, the solder mask layer being coupled with the one or more build-up layers and having openings disposed in the solder mask layer to allow coupling of package-level interconnect structures with the electrical routing features through the one or more openings. Other embodiments may be described and/or claimed.

公开(公告)号：US09642248B2

公开(公告)日：2017-05-02

申请号：US14618235

申请日：2015-02-10

Applicant: Intel Corporation

Inventor： Qing Ma ,  Johanna M. Swan ,  Robert Starkston ,  John S. Guzek ,  Robert L. Sankman ,  Aleksandar Aleksov

IPC: H05K1/00 ,  H05K1/03 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H05K1/18 ,  H05K3/46 ,  H01L21/56 ,  H01L21/48 ,  H05K1/02 ,  H05K1/11

CPC classification number: H01L23/5386 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08238 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/185 ,  H05K3/4688 ,  H05K2201/017 ,  H05K2203/1469 ,  Y10T156/1057 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.

公开(公告)号：US20160322290A1

公开(公告)日：2016-11-03

申请号：US15205223

申请日：2016-07-08

Applicant: Intel Corporation

Inventor： Qing Ma ,  Chuan Hu ,  Patrick Morrow

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49822 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05442 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15788 ,  H01L2924/16251 ,  H05K3/42 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/096 ,  Y10T156/10 ,  H01L2924/00

Abstract: Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.

Abstract translation: 公开了用于集成电路（IC）装置的基板的实施例。 衬底包括由已经结合在一起的两个或更多个离散的玻璃层组成的芯。 可以在相邻的玻璃层之间设置单独的粘合层，以将这些层连接在一起。 衬底还可以包括在多层玻璃芯的相对侧上或者可能在芯的一侧上的堆积结构。 导电端子可以形成在基板的两侧，并且IC管芯可以与基板的一侧上的端子耦合。 相对侧上的端子可以与诸如电路板的下一级组件耦合。 一个或多个导体延伸通过多层玻璃芯，并且一个或多个导体可以与布置在芯上的积聚结构电耦合。 描述和要求保护其他实施例。

公开(公告)号：US20160020051A1

公开(公告)日：2016-01-21

申请号：US14368771

申请日：2013-12-17

Applicant: INTEL CORPORATION

Inventor： Qing Ma ,  Johanna Swan ,  Valluri Rao ,  Feras Eid

IPC: H01H59/00 ,  H01Q5/314 ,  H01H50/00

CPC classification number: H01H59/0009 ,  H01H50/005 ,  H01H2229/016 ,  H01H2229/05 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01Q5/314

Abstract: An electronic device and methods including a switch formed in a chip package are shown. An electronic device and methods including a switch formed in a polymer based dielectric are shown. Examples of switches shown include microelectromechanical system (MEMS) structures, such as cantilever switches and/or shunt switches.

Abstract translation: 示出了包括形成在芯片封装中的开关的电子装置和方法。 示出了包括形成在基于聚合物的电介质中的开关的电子装置和方法。 所示的开关的示例包括微机电系统（MEMS）结构，例如悬臂开关和/或分流开关。