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    Phase multiplexer
    21.
    发明授权
    Phase multiplexer 有权
    相位多路复用器

    公开(公告)号：US09438265B2

    公开(公告)日：2016-09-06

    申请号：US14155327

    申请日：2014-01-14

    Applicant: Intel Corporation

    Inventor： Paolo Madoglio ,  Stefano Pellerano

    IPC: G06F1/04 ,  H03M1/82 ,  G06F1/08 ,  H03M1/08 ,  H03M1/66 ,  H03K5/13 ,  H03L7/16 ,  H03K5/00

    CPC classification number: H03M1/822 ,  G06F1/04 ,  G06F1/08 ,  H03K5/131 ,  H03K2005/00045 ,  H03L7/16 ,  H03M1/0836 ,  H03M1/662

    Abstract: Representative implementations of devices and techniques provide a phase multiplexer that may be associated with at least a communication device. The described phase multiplexer may be able to switch between input phases without distorting a pulse width of a given input phase. In one implementation, this is achieved by enabling one phase at a time. More specifically, a gating window specific for each given phase is provided. The gating window is designed to avoid glitches associated with signals at an output of the phase multiplexer. Furthermore, the gating window is designed to avoid the generation of pulse width modifications.

    Abstract translation: 设备和技术的代表性实现提供了可以与至少一个通信设备相关联的相位多路复用器。 所描述的相位多路复用器可能能够在输入相位之间切换，而不会使给定输入相位的脉冲宽度变形。 在一个实现中，这是通过一次启用一个阶段来实现的。 更具体地，提供对于每个给定相位特定的门控窗口。 门控窗口旨在避免与相位多路复用器输出端的信号相关的毛刺。 此外，门控窗口被设计为避免产生脉冲宽度修改。

    Technologies for on-circuit board de-embedding
    22.
    发明授权
    Technologies for on-circuit board de-embedding 有权

    公开(公告)号：US12259430B1

    公开(公告)日：2025-03-25

    申请号：US17871414

    申请日：2022-07-22

    Applicant: Intel Corporation

    Inventor： Bishnu Prasad Patra ,  Stefano Pellerano

    IPC: G01R31/28 ,  H05K1/02 ,  H01L23/00

    Abstract: Technologies for on-circuit board de-embedding are disclosed. In the illustrative embodiment, several micromechanical relays on a circuit board can connect a trace on the circuit board to an open circuit, a closed circuit, a load circuit, or a through circuit. For the through circuit, the trace is connected to an integrated circuit component mounted on the circuit board. A cable is connected to the trace, allowing for signals to be sent to any of the four circuits without any probes connected to the circuit board. The transmitted and/or reflected signals can be measured, which can be used to de-embed the integrated circuit component.

    Scalable gate control in quantum circuit assemblies
    23.
    发明授权
    Scalable gate control in quantum circuit assemblies 有权

    公开(公告)号：US12248848B2

    公开(公告)日：2025-03-11

    申请号：US17340173

    申请日：2021-06-07

    Applicant: Intel Corporation

    Inventor： Sushil Subramanian ,  Stefano Pellerano ,  Ravi Pillarisetty ,  Jong Seok Park ,  Todor M. Mladenov

    IPC: G06N10/00 ,  H03M1/66

    Abstract: Quantum circuit assemblies that employ active pulse shaping in order to be able to control states of a plurality of qubits with signal pulses propagated over a shared signal propagation channel are disclosed. An example quantum circuit assembly includes a quantum circuit component that includes a first qubit, associated with a first frequency to control the state of the first qubit, and a second qubit, associated with a second frequency to control the state of the second qubit. A shared transmission channel is coupled to the first and second qubits. The assembly further includes a signal pulse generation circuit, configured to generate a signal pulse to be propagated over the shared transmission channel to control the state of the first qubit, where the signal pulse has a center frequency at the first frequency, a bandwidth that includes the second frequency, and a notch at the second frequency.

    Closed-loop baud rate carrier and carrier frequency tuning for wireless chip-to-chip interface
    24.
    发明授权
    Closed-loop baud rate carrier and carrier frequency tuning for wireless chip-to-chip interface 有权

    公开(公告)号：US12212510B2

    公开(公告)日：2025-01-28

    申请号：US17124536

    申请日：2020-12-17

    Applicant: Intel Corporation

    Inventor： Peter Sagazio ,  Chun C. Lee ,  Stefano Pellerano ,  Christopher D. Hull

    IPC: H04L5/00 ,  H04B1/10

    Abstract: Various aspects of this disclosure provide a receiver. The receiver may include a down-converter configured to down-convert a received communication signal at a predefined carrier frequency, with a reference signal received from a reference signal generator, and a processor configured to perform a signal quality detection to identify a signal quality metric of the received communication signal at the predefined carrier frequency, and to provide a frequency adjusting signal to the reference signal generator to change the frequency of the reference signal based on the performed signal quality detection to identify the signal quality metric of the received communication signal at the predefined carrier frequency.

    ANTENNA MODULES WITH PARTIALLY OVERLAPPING STACKED CIRCUITS
    25.
    发明申请
    ANTENNA MODULES WITH PARTIALLY OVERLAPPING STACKED CIRCUITS 有权

    公开(公告)号：US20250006719A1

    公开(公告)日：2025-01-02

    申请号：US18341875

    申请日：2023-06-27

    Applicant: Intel Corporation

    Inventor： Georgios Panagopoulos ,  Richard Geiger ,  Steven Callender ,  Georgios Dogiamis ,  Manisha Dutta ,  Stefano Pellerano

    IPC: H01L25/18 ,  H01L23/00 ,  H01Q1/22 ,  H01Q23/00

    Abstract: Example antenna module includes antenna units provided over an antenna unit support, and ICs communicatively coupled to various antenna units. The ICs are arranged in two or more subsets of one or more ICs in each subset, where an individual IC belongs to only one subset, different subsets are in different layers with respect to the antenna unit support, and an average pitch of projections of all of the ICs onto a plane parallel to the antenna unit support is substantially equal to, or smaller, than an average pitch of the antenna units. When an average width of the ICs is larger than the average pitch of the antenna units, arranging the ICs in two or more subsets in different layers means that at least one of the ICs of one subset partially overlaps with at least one of the ICs of another subset.

    TECHNOLOGIES FOR SIGNAL CONDITIONING OF SIGNALS FOR QUBITS
    28.
    发明公开
    TECHNOLOGIES FOR SIGNAL CONDITIONING OF SIGNALS FOR QUBITS 审中-公开

    公开(公告)号：US20230153125A1

    公开(公告)日：2023-05-18

    申请号：US17527875

    申请日：2021-11-16

    Applicant: Intel Corporation

    Inventor： Sushil Subramanian ,  Stefano Pellerano ,  Todor Mladenov ,  JongSeok Park

    IPC: G06F9/448 ,  G06N10/00

    CPC classification number: G06F9/4498 ,  G06N10/00

    Abstract: Technologies for signal conditioning for signals for qubits are disclosed. In the illustrative embodiment, a finite impulse response filter is applied to a control signal for a target qubit to filter out a frequency corresponding to a collateral qubit. An infinite impulse response filter is then applied to the signal after the finite impulse response filter, which amplifies some of the frequencies filtered out by the finite impulse response, narrowing the bandwidth that is filtered out. Such an approach reduces the attenuation of the signal and can be used to reduce memory requirements of quantum/classical interface circuitry.

    QUADRATURE LOCAL OSCILLATOR SIGNAL GENERATION SYSTEMS AND METHODS
    29.
    发明申请
    QUADRATURE LOCAL OSCILLATOR SIGNAL GENERATION SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20200295765A1

    公开(公告)日：2020-09-17

    申请号：US16352043

    申请日：2019-03-13

    Applicant: Intel Corporation

    Inventor： Abhishek Agrawal ,  Alon Cohen ,  Gil Horovitz ,  Somnath Kundu ,  Run Levinger ,  Stefano Pellerano ,  Jahnavi Sharma ,  Evgeny Shumaker ,  Izhak Hod

    IPC: H03L7/081 ,  H03L7/083

    Abstract: A quadrature based voltage controlled oscillator (VCO) local oscillator (LO) system is disclosed. The system includes a phase detector, a quadrature phase VCO, a quadrature control path, an in-phase control path, and an in-phase VCO. The phase detector is configured to compare and generate phase error between a reference clock and an in-phase VCO output. The quadrature control path configured to generate a quadrature control voltage based on a quadrature VCO output and the in-phase VCO output. The quadrature phase VCO configured to generate the quadrature VCO output based on the quadrature control voltage and the generated phase error. The in-phase control path configured to generate an in-phase control voltage based on the quadrature VCO output and the in-phase VCO output. The in-phase VCO is configured to generate the in-phase VCO output based on the in-phase control voltage and the generated phase error. An all digital dual mode phase locked/phase tracking loop LO generate system is also disclosed.

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