公开(公告)号：US20240219660A1

公开(公告)日：2024-07-04

申请号：US18089934

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Hongxia Feng ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Eric J.M. Moret ,  Robert Alan May ,  Srinivas Venkata Ramanuja Pietambaram ,  Tarek A. Ibrahim ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Bin Mu

IPC: G02B6/42 ,  G02B5/10

CPC classification number: G02B6/4246 ,  G02B5/10 ,  G02B6/4274

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240219655A1

公开(公告)日：2024-07-04

申请号：US18089916

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Bai Nie ,  Brandon C. Marin ,  Dingying Xu ,  Gang Duan ,  Hongxia Feng ,  Jeremy D. Ecton ,  Kristof Darmawikarta ,  Kyle Jordan Arrington ,  Srinivas Venkata Ramanuja Pietambaram ,  Xiaoying Guo ,  Yiqun Bai ,  Ziyin Lin

IPC: G02B6/42 ,  H01L21/48

CPC classification number: G02B6/4214 ,  H01L21/4803 ,  H01L23/49827

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US11749585B2

公开(公告)日：2023-09-05

申请号：US16805392

申请日：2020-02-28

Applicant: Intel Corporation

Inventor： Yiqun Bai ,  Vipul Mehta ,  John Decker ,  Ziyin Lin

IPC: H01L23/31 ,  H01L23/433 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/4334 ,  H01L21/56 ,  H01L23/3185 ,  H01L25/0655 ,  H01L25/50

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a mold material layer abutting electronic substrate and substantially surrounding the at least one integrated circuit, and at least one structure within the mold material layer, wherein the at least one structure comprises a material having a modulus of greater than about 20 gigapascals and a thermal conductivity of greater than about 10 watts per meter-Kelvin.

公开(公告)号：US20200227332A1

公开(公告)日：2020-07-16

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, JR.

IPC: H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

公开(公告)号：US10115606B2

公开(公告)日：2018-10-30

申请号：US15139265

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Yiqun Bai ,  Yuying Wei ,  Arjun Krishnan ,  Suriyakala Ramalingam ,  Yonghao Xiu ,  Beverly J. Canham ,  Sivakumar Nagarajan ,  Saikumar Jayaraman ,  Nisha Ananthakrishnan

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/28 ,  H01L21/56 ,  H01L23/29 ,  H01L23/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.

公开(公告)号：US09704767B1

公开(公告)日：2017-07-11

申请号：US14998368

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Suriyakala Ramalingam ,  Yiqun Bai ,  Nisha Ananthakrishnan ,  Arjun Krishnan

IPC: H01L23/29 ,  H01L21/56 ,  H01L23/16 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L21/4853 ,  H01L23/15 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: Techniques and mechanisms for mitigating warpage of structures in a package. In an embodiment, a packaged integrated circuit device includes a mold compound disposed at least partially around an integrated circuit chip. The mold compound comprises fibers suspended in a media that is to aid in mechanical reinforcement of such fibers. The reinforced fibers contribute to mold compound properties that resist warping of the IC chip that might otherwise take place as a result of solder reflow or other processing. A modulus of elasticity of the mold compound is equal to or more than three GigePascals (3 GPa), where the modulus of elasticity corresponds to a temperature equal to two hundred and sixty degrees Celsius (260° C.). In another embodiment, a spiral flow value of the mold compound is equal to or more than sixty five centimeters (65 cm).

公开(公告)号：US09431274B2

公开(公告)日：2016-08-30

申请号：US13722886

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Suriyakala Ramalingam ,  Manish Dubey ,  Hsin-Yu Li ,  Michelle S. Phen ,  Hitesh Arora ,  Nisha Ananthakrishnan ,  Yiqun Bai ,  Yonghao Xiu ,  Rajendra C. Dias

IPC: H01L21/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L21/563 ,  H01L23/295 ,  H01L24/09 ,  H01L24/17 ,  H01L24/29 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/29386 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于具有以通常随机分布图案排列的填充颗粒的底部填充层的集成电路（IC）封装的技术和配置。 在一些实施例中，通过对IC封装组件的一个或多个部件上的静电电荷，通过对填料进行表面处理以减少填充剂电荷，可以通过施加电力来抵抗填料颗粒的大致随机分布图案 通过使用相对较低的最大填充剂粒度的底部填充材料和/或通过在相对低的温度下快速固化底部填充层，使底部填充材料的填料颗粒在与重力方向相反的方向上。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09230833B2

公开(公告)日：2016-01-05

申请号：US14638328

申请日：2015-03-04

Applicant: INTEL CORPORATION

Inventor： Manish Dubey ,  Rajendra C. Dias ,  Yonghao Xiu ,  Arjun Krishnan ,  Yiqun Bai ,  Purushotham Kaushik Muthur Srinath

IPC: H01L21/56 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L23/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particless within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.

Abstract translation: 本说明书的实施例包括在微电子器件上处理底部填充材料之后将微电子器件附着到具有互连结构的微电子衬底的方法，其中，在将微电子器件连接到微电子器件之前，底部填充材料内的填料颗粒可能被排除离开互连结构 器件到微电子结构。 这些方法可以包括在互连结构上引入电荷，并且可以包括将互连结构放置在相对的板之间，并且在将底部填充材料沉积在互连结构上之后在相对的板之间产生偏压。

公开(公告)号：US20250112161A1

公开(公告)日：2025-04-03

申请号：US18478538

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Minglu Liu ,  Seyyed Yahya Mousavi ,  Yingying Zhang ,  Gang Duan ,  Andrey Gunawan ,  Yosuke Kanaoka ,  Yiqun Bai ,  Ziyin Lin ,  Bohan Shan ,  Dingying Xu ,  Srinivas Pietambaram ,  Hong Seung Yeon

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31

Abstract: Methods and apparatus to connect interconnect bridges to package substrates are disclosed. An example package substrate includes a dielectric layer including a cavity, a first contact pad positioned in the cavity, a first semiconductor die including a second contact pad and a third contact pad, the second contact pad positioned on a first surface of the first semiconductor die, the third contact pad positioned on a second surface of the first semiconductor die, the second surface opposite the first surface, the second contact pad coupled to the first contact pad, the third contact pad to be coupled to a second semiconductor die, and a non-conductive material surrounding the first contact pad and the second contact pad.

公开(公告)号：US20240222304A1

公开(公告)日：2024-07-04

申请号：US18148148

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Jiaqi Wu ,  Haobo Chen ,  Srinivas Pietambaram ,  Bai Nie ,  Gang Duan ,  Kyle Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/00 ,  H01L23/538

CPC classification number: H01L24/16 ,  H01L23/538 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L25/16

Abstract: Methods and apparatus to reduce solder bump bridging between two substrates. An apparatus includes a first substrate including a first bump and a second bump spaced apart from the first bump, the first bump including a first base, the second bump including a second base; and a second substrate including a third bump and a fourth bump spaced apart from the third bump, the third bump including a third base, the fourth bump including a fourth base, the first base electrically coupled to the third base by first solder, the second base electrically coupled to the fourth base by second solder, the first solder having a first volume, the second solder having a second volume, the first volume less than the second volume.