公开(公告)号：US20220102263A1

公开(公告)日：2022-03-31

申请号：US17459296

申请日：2021-08-27

Applicant: Infineon Technologies AG

Inventor： Chee Yang Ng ,  Stefan Woetzel ,  Edward Fuergut ,  Thai Kee Gan ,  Chee Hong Lee ,  Jayaganasan Narayanasamy ,  Ralf Otremba

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.

公开(公告)号：US20200039820A1

公开(公告)日：2020-02-06

申请号：US16595532

申请日：2019-10-08

Applicant: Infineon Technologies AG

Inventor： Claus Waechter ,  Edward Fuergut ,  Bernd Goller ,  Michael Ledutke ,  Dominic Maier

IPC: B81C1/00 ,  B81B7/00

Abstract: The method comprises fabricating a semiconductor panel comprising a plurality of semiconductor devices, fabricating a cap panel comprising a plurality of caps, bonding the cap panel onto the semiconductor panel so that each one of the caps covers one or more of the semiconductor devices, and singulating the bonded panels into a plurality of semiconductor modules.

公开(公告)号：US10435292B2

公开(公告)日：2019-10-08

申请号：US15651522

申请日：2017-07-17

Applicant: Infineon Technologies AG

Inventor： Claus Waechter ,  Edward Fuergut ,  Bernd Goller ,  Michael Ledutke ,  Dominic Maier

IPC: H01L27/14 ,  B81C1/00 ,  B81B7/00

Abstract: The method comprises fabricating a semiconductor panel comprising a plurality of semiconductor devices, fabricating a cap panel comprising a plurality of caps, bonding the cap panel onto the semiconductor panel so that each one of the caps covers one or more of the semiconductor devices, and singulating the bonded panels into a plurality of semiconductor modules.

公开(公告)号：US20180350780A1

公开(公告)日：2018-12-06

申请号：US16047688

申请日：2018-07-27

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Holger Doepke ,  Olaf Hohlfeld ,  Michael Juerss

IPC: H01L25/07

CPC classification number: H01L25/072 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/552 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/03462 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48491 ,  H01L2224/73265 ,  H01L2224/83951 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18301 ,  H05K3/282 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2203/1316 ,  H05K2203/1322 ,  H05K2203/1377 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: An electronic device package includes a semiconductor chip having a contact pad on a main face of the semiconductor chip, a contact element disposed on the contact pad, a dielectric layer disposed on the semiconductor chip and the contact element, and an encapsulant disposed onto the dielectric layer.

公开(公告)号：US10115646B2

公开(公告)日：2018-10-30

申请号：US15149207

申请日：2016-05-09

Applicant: Infineon Technologies AG

Inventor： Juergen Hoegerl ,  Edward Fuergut

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/04 ,  H01L23/10 ,  H01L23/492 ,  H01L23/14 ,  H01L23/29 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L29/739 ,  H01L29/868 ,  H01L23/544 ,  H01L23/00

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement may include an electrically conductive plate having a surface, a plurality of power semiconductor devices arranged on the surface of the electrically conductive plate, wherein a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices may be electrically coupled to the electrically conductive plate, a plurality of electrically conductive blocks, wherein each electrically conductive block may be electrically coupled with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and encapsulation material encapsulating the plurality of power semiconductor devices, wherein at least one edge region of the surface of the electrically conductive plate may be free from the encapsulation material.

公开(公告)号：US09768037B2

公开(公告)日：2017-09-19

申请号：US14279752

申请日：2014-05-16

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Edward Fuergut ,  Irmgard Escher-Poeppel

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L23/31 ,  H01L23/433 ,  H01L23/552 ,  H01L21/683 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/538 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68318 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A method of manufacturing an electronic device package includes structuring a metal layer to generate a structured metal layer having a plurality of openings. Semiconductor chips are placed into at least some of the openings. An encapsulating material is applied over the structured metal layer and the semiconductor chips to form an encapsulation body. The encapsulation body is separated into a plurality of electronic device packages.

公开(公告)号：US20170263480A1

公开(公告)日：2017-09-14

申请号：US15607735

申请日：2017-05-30

Applicant: Infineon Technologies AG

Inventor： Michael Ledutke ,  Edward Fuergut

IPC: H01L21/673 ,  H01L23/31 ,  H01L21/56 ,  H01L21/66

CPC classification number: H01L23/3107 ,  H01L21/561 ,  H01L21/67336 ,  H01L22/10 ,  H01L22/32 ,  H01L23/3121 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In various embodiments, an arrangement is provided. The arrangement may include a plurality of chips; a chip carrier carrying the plurality of chips, the chip carrier including a chip carrier notch; and encapsulation material encapsulating the chip carrier and filling the chip carrier notch; wherein the outer circumference of the encapsulation material is free from a recess.

公开(公告)号：US20170178993A1

公开(公告)日：2017-06-22

申请号：US15382693

申请日：2016-12-18

Applicant: Infineon Technologies AG

Inventor： Thorsten MEYER ,  Edward Fuergut ,  Gerald Ofner ,  Petteri Palm

IPC: H01L23/31 ,  H01L21/78 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3157 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/00 ,  H01L24/09 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81191 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An electronic component which comprises an electrically insulating layer having at least one through hole, a patterned electrically conductive structure at least partially on the electrically insulating layer, an electronic chip electrically coupled with the patterned electrically conductive structure, an encapsulant at least partially encapsulating the electronic chip, and at least one electrically conductive contact structure at least partially in the at least one through hole in contact with at least part of the patterned electrically conductive structure.

公开(公告)号：US20170076961A1

公开(公告)日：2017-03-16

申请号：US15361108

申请日：2016-11-25

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/56 ,  H01L27/02 ,  H01L23/498 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.

Abstract translation: 提供了一种安排。 该布置可以包括：具有前侧和后侧的基板，基板内的管芯区域，限定管芯区域的背面的多用途层以及设置在多用途层之间的蚀刻停止层， 多用途层和背面。 多用途层可以由欧姆材料形成，并且蚀刻停止层可以是第一掺杂浓度的第一导电类型。

公开(公告)号：US09595502B2

公开(公告)日：2017-03-14

申请号：US14926258

申请日：2015-10-29

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Edward Fuergut ,  Horst Groeninger ,  Juergen Hoegerl

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/433 ,  H01L29/739 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/72 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/433 ,  H01L24/83 ,  H01L29/7393 ,  H01L2924/351

Abstract: A semiconductor assembly is described. In accordance with one example of the invention, the semiconductor assembly comprises a semiconductor body, a top main electrode arranged on a top side, a bottom main electrode arranged on an underside, and a control electrode arranged on the top side. The semiconductor assembly further includes a spring element for the pressure contacting of the control electrode with a pressure force generated by the spring element.

Abstract translation: 描述半导体组件。 根据本发明的一个示例，半导体组件包括半导体主体，布置在顶侧的顶部主电极，设置在下侧的底部主电极和布置在顶侧的控制电极。 半导体组件还包括用于使控制电极与弹簧元件产生的压力的压力接触的弹簧元件。